Claims
- 1. A method of manufacturing a semiconductor memory device, comprising the steps of:
- forming a first conductive layer (1c) having peripheral portions covered with an insulating film on a main surface of a semiconductor substrate (40) on which an insulating film (13) for isolating elements are formed, and forming a pair of impurity regions (6, 6) on the main surface of said.semiconductor substrate;
- forming an insulating film (10c) on a surface of said impurity region;
- forming a second conductive layer (11a) on said insulating film and on said insulating film for isolating elements;
- patterning said second conductive layer to form an opening portion deep enough to reach a surface of one of said impurity regions;
- forming a first dielectric layer (10a) on said second conductive layer to cover a surface of said second conductive layer;
- forming a third conductive layer (9) on the surface of said impurity region exposed/on said first conductive layer and in said opening portion and patterning the same into a prescribed shape so as to expose a portion of said first dielectric layer;
- forming a second dielectric layer (10b) on said third conductive layer and said exposed first dielectric layer to cover the surface of said third conductive layer;
- selectively removing said first and second dielectric layers to expose a portion of a surface of said second conductive layer; and
- forming a fourth conductive layer (11b) on said second dielectric layer and on the surface of said exposed second conductive layer.
Priority Claims (1)
Number |
Date |
Country |
Kind |
63-312420 |
Dec 1988 |
JPX |
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Parent Case Info
This application is a division of application Ser. No. 07/446,744, filed Dec. 6, 1989.
US Referenced Citations (8)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0295709 |
Jun 1988 |
EPX |
0022057 |
Jan 1988 |
JPX |
0197368 |
Aug 1988 |
JPX |
Non-Patent Literature Citations (2)
Entry |
IEDM Publication entitled "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS," by T. Ema et al., 1988, pp. 592-595. |
T. Kisu, "A Novel Storage Capacitance Enlargement Structure Using a Double-Stacked Storage Node In STC Dram Cell", 20th Int'l. Conference on Solid State Devices and Materials, 1988, pp. 581-584. |
Divisions (1)
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Number |
Date |
Country |
Parent |
446744 |
Dec 1989 |
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