Royannez et al. "A 1.0ns 64-Bits GaAs Adder Using Quad Tree Algorithm," IEEE, pp. 24-28, Mar. 1996. |
Kim et al. "A Timing-Driven Data Path Layout Synthesis with Integer Programming," IEEE, pp. 716-719, Nov. 1995. |
Usami et al "Hierarchical Symbolic Design Methodology for Large-Scale Data Paths," IEEE, pp. 381-385, Mar. 1991. |
Brewer et al "Interconnection Synthesis with Geometric Constraints," IEEE, pp. 158-165, Nov. 1990. |
Tsujihashi et al "A High-Density Data-Path Generator with Stretchable Cells," IEEE, pp. 2-8, Jan. 1994. |
Rijnders et al "Timing Optimization by Bit-Level Arithmatic Transformations," IEEE, pp. 48-53, Nov. 1995. |