Patent Application
20240250084
The present invention generally relates to relates to a method for optimizing protection circuits of electronic device chips in a wafer. More specifically, the present invention relates to a method for wafer-level optimization of protection circuits of nitride-based electronic device chips in a wafer.
Wide bandgap materials, such as gallium nitride (GaN) have been widely used for high-power and high-frequency devices because of their low power loss and fast switching transition in comparison with silicon (Si) metal oxide semiconductor (MOS) materials. For example, GaN field effect transistors (FET) have been widely used in making power devices in fast chargers for mobile devices. As nitride-based transistors have lower threshold voltages, they are vulnerable to high voltage damages such as electrostatic discharges (ESD). Conventionally, a nitride-based transistor Qm may be protected with a protection circuit as shown in
One objective of the present invention is to provide a cost-effective approach to address the above-said issues of non-uniform threshold voltage distribution within a wafer so as to improve the fabrication yield.
In according with one aspect of the present disclosure, a method for wafer-level optimization of protection circuits of nitride-based electronic device chips in a wafer is provided. The method comprises: fabricating an adjustment circuit in the wafer for each of the protection circuits, the adjustment circuit including one or more fuse elements connected respectively in parallel with one or more protection devices in the protection circuit; and adjusting each of the protection circuits by trimming one or more to-be-trimmed fuse elements corresponding to the protection circuit. The trimming of the to-be-trimmed fuse elements is performed by applying a photoresist layer on the wafer; patterning the photoresist layer with a one-to-one (1:1) photomask to expose the to-be-trimmed fuse elements; and etching away the to-be-trimmed fuse elements.
By using the 1:1 photomask, complete wafer coverage can be achieved without stepping the wafer repeatedly from position to position under an optical column. Therefore, complexity of photomask alignment can be greatly reduced and exposure errors can be minimized.
Aspects of the present disclosure may be readily understood from the following detailed description with reference to the accompanying figures. The illustrations may not necessarily be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. For simplicity, common reference numerals may be used throughout the drawings and the detailed description to indicate the same or similar components.
In the following description, preferred examples of the present disclosure will be set forth as embodiments which are to be regarded as illustrative rather than restrictive. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.
As shown in
S202: fabricating an adjustment circuit in the wafer for each of the protection circuits, the adjustment circuit including one or more fuse elements connected respectively in parallel with one or more protection devices in the protection circuit;
S204: adjusting each of the protection circuits by trimming one or more to-be-trimmed fuse elements corresponding to the protection circuit.
In some embodiments, the trimming of to-be-trimmed fuse elements may be performed by: applying a photoresist layer on the wafer; patterning the photoresist layer with a one-to-one (1:1) photomask (i.e., with a 1× photomask magnification), to expose the to-be-trimmed fuse elements; and etching away the to-be-trimmed fuse elements.
The 1:1 photomask is formed to expose the to-be-trimmed fuse elements based on a threshold voltage distribution of the wafer. In particular, the wafer may be divided into one or more regions based on the threshold voltage distribution. Accordingly, the photomask can be formed such that quantity of to-be-trimmed fuse elements for a protection circuit in a region including transistors of lower threshold voltage is greater than quantity of to-be-trimmed fuse elements for a protection circuit in a region including transistors of higher threshold voltage.
In some embodiments, the trimming of the to-be-trimmed fuse elements may be performed just after forming the fuse elements. In some embodiments, the trimming of the to-be-trimmed fuse elements may be performed after depositing a passivation layer on top of fuse elements. As such, structures other that those to-be-trimmed fuse elements can be protected by the passivation layer during the trimming process.
In some embodiments, the fuse elements may be made of polysilicon. In some embodiments, the fuse elements may be made of metals including, but not limited to, titanium (Ti), Tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), cuprum (Cu), nickel (Ni), platinum (Pt), plumbum (Pb), molybdenum (Mo) and compounds (for example but not limited to, titanium nitride (TlN), tantalum nitride (TaN), other conductive nitrides or conductive oxides) thereof, metal alloys (for example aluminum copper alloy (Al—Cu)), or other proper materials.
The threshold voltage distribution of the wafer may be a function of distance from the center of the wafer. For example, the nitride-based main transistor Qm_1 in the region 30_1, which is located within a central area of the wafer, may have a relatively low threshold voltage Vth1. The nitride-based main transistor Qm_N in the region 30_N, which is located in an outermost peripheral area of the wafer, may have a relatively high threshold voltage VthN.
In some embodiments, the relationship between the threshold voltage values Vth_i (i=1, 2, . . . , N) may be given by Vthi+1=Vthi+ΔV, where ΔV is a difference between threshold voltage value of transistors located in any two adjacent regions.
Each of the nitride-based main transistors Qm_1 may be protected with a protection circuit 320_1. The protection circuit 320_1 may include a discharge-control transistor QDIS_1 and a plurality of rectifiers D1_1, D1_2, . . . , D1_M connected in series between a gate of the main transistor Qm_1 and a gate of the discharge-control transistor QDIS_1. The plurality of rectifiers D1_1, D1_2, . . . , D1_M may include a first rectifier D1_1 having an anode connected to the gate of the main transistor Qm_1 and a last rectifier D1_M having a cathode connected to the gate of the discharge-control transistor QDIS_1.
Each of the electronic device chips 300_1 may further have an adjustment circuit including one or more fuse elements F1_1, F1_2, . . . , F1_K connected respectively in parallel with one or more rectifiers in the protection circuit, where K is the number of fuse elements. In some embodiments, K may be equal to M, that is, all of the rectifiers D1_1, D1_2, . . . , D1_M are connected respectively in parallel with a fuse element for circuit optimization. In other embodiments, K may be less than M, that is, only a portion of the rectifiers D1_1, D1_2, . . . , D1_M are connected respectively in parallel with a fuse element for circuit optimization.
Similarly, each of the nitride-based main transistors Qm_N may be protected with a protection circuit 320_N. The protection circuit 320_N may include a discharge-control transistor QDIS_N and one or more rectifiers DN_1, DN_2, . . . , DN_M connected in series between a gate of the main transistor Qm_N and a gate of the discharge-control transistor QDIS_N. The plurality of rectifiers DN_1, DN_2, . . . , DN_M may include a first rectifier DN_1 having an anode connected to the gate of the main transistor Qm_N and a last rectifier DN_M having a cathode connected to the gate of the discharge-control transistor QDIS_N.
Each of the electronic device chips 300_N may have an adjustment circuit including one or more fuse elements FN_1, FN_2, . . . , FN_K connected respectively in parallel with one or more rectifiers in the protection circuit, where K is the number of fuse elements. In some embodiments, K may be equal to M, that is, all of the rectifiers DN_1, DN_2, . . . , DN_M are connected respectively in parallel with a fuse element for circuit optimization. In other embodiments, K may be less than M, that is, only a portion of the rectifiers DN_1, DN_2, . . . , DN_M are connected respectively in parallel with a fuse element for circuit optimization.
In some embodiments, each of the main transistors may be a AlGaN/GaN enhancement-mode (E-mode) high-electron-mobility transistor (HEMT).
In some embodiments, each of the discharge-control transistors may be a AlGaN/GaN enhancement-mode (E-mode) high-electron-mobility transistor (HEMT).
In some embodiments, each of the rectifiers may comprise a transistor having a gate being shorted with a source to act as an anode of the rectifier and a drain to act as a cathode of the rectifier. Each of the transistors may be a AlGaN/GaN enhancement-mode (E-mode) high-electron-mobility transistor (HEMT).
As it can be seen from the examples in
The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations. While the apparatuses disclosed herein have been described with reference to particular structures, shapes, materials, composition of matter and relationships . . . etc., these descriptions and illustrations are not limiting. Modifications may be made to adapt a particular situation to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/101998 | 6/28/2022 | WO |
