Patent Application
20230253939
The present invention is related to circuit design, and more particularly, to a method for performing common mode voltage re-biasing in an analog front-end circuit of a receiver, an associated common mode voltage re-biasing circuit, the receiver and an associated integrated circuit (IC).
According to the related art, different stages of circuits in a conventional analog front-end circuit may have different common mode voltages, respectively, to allow subsequent circuit to operate in a suitable voltage range. However, certain problems may occur. For example, when a system manufacturer tries to implement electronic products conforming to newer communications specifications, the existing circuit characteristics of the conventional analog front-end circuit may make the whole system be unable to simultaneously meeting various requirements, which may result in test failures. Therefore, there is a need for a novel method and associated architecture to implement electronic products conforming to newer communications specifications without introducing side effects, or in a way that is less likely to introduce a side effect.
An object of the present invention is to provide a method for performing common mode voltage re-biasing in an analog front-end circuit of a receiver, an associated common mode voltage re-biasing circuit, the receiver and an associated IC, in order to solve the problems mentioned above.
Another object of the present invention is to provide a method for performing common mode voltage re-biasing in an analog front-end circuit of a receiver, an associated common mode voltage re-biasing circuit, the receiver and an associated IC, in order to achieve optimal performance of an electronic product.
At least one embodiment of the present invention provides a common mode voltage re-biasing circuit for performing common mode voltage re-biasing in an analog front-end circuit of a receiver. The common mode voltage re-biasing circuit may comprise a control circuit and multiple switchable common mode voltage re-biasing sub-circuits that are coupled to the control circuit, and the multiple switchable common mode voltage re-biasing sub-circuits may comprise a first switchable common mode voltage re-biasing sub-circuit and a second switchable common mode voltage re-biasing sub-circuit. The control circuit can be configured to generate at least one control signal according to a command, for controlling the common mode voltage re-biasing circuit to operate in a selected circuit configuration. In addition, the multiple switchable common mode voltage re-biasing sub-circuits can be configured to select a predetermined circuit configuration from a first predetermined circuit configuration and a second predetermined circuit configuration according to the at least one control signal to be the selected circuit configuration to perform common mode voltage re-biasing operations corresponding to the selected circuit configuration, respectively. For example, the first switchable common mode voltage re-biasing sub-circuit can be positioned in the analog front-end circuit of the receiver and coupled to a first differential input terminal of the receiver, and the second switchable common mode voltage re-biasing sub-circuit can be positioned in the analog front-end circuit of the receiver and coupled to a second differential input terminal of the receiver.
According to some embodiments, the present invention further provides the receiver comprising the above-mentioned common mode voltage re-biasing circuit, wherein the receiver may comprise: a physical layer (PHY) circuit, wherein the PHY circuit comprises the common mode voltage re-biasing circuit; and an upper layer circuit, configured to select a predetermined communications mode from a plurality of predetermined communications modes to be a selected communications mode, and send the command according to the selected communications mode, to make the selected circuit configuration correspond to the selected communications mode.
According to some embodiments, the present invention further provides an IC comprising the above-mentioned receiver.
At least one embodiment of the present invention provides a method for performing common mode voltage re-biasing in an analog front-end circuit of a receiver. The method may comprise: generating at least one control signal according to a command, for controlling a common mode voltage re-biasing circuit to operate in a selected circuit configuration; and utilizing multiple switchable common mode voltage re-biasing sub-circuits of the common mode voltage re-biasing circuit to select a predetermined circuit configuration from a first predetermined circuit configuration and a second predetermined circuit configuration according to the at least one control signal to be the selected circuit configuration to perform common mode voltage re-biasing operations corresponding to the selected circuit configuration, respectively, wherein the multiple switchable common mode voltage re-biasing sub-circuits comprise a first switchable common mode voltage re-biasing sub-circuit and a second switchable common mode voltage re-biasing sub-circuit, and the first switchable common mode voltage re-biasing sub-circuit and the second switchable common mode voltage re-biasing sub-circuit are positioned in the analog front-end circuit of the receiver and are coupled to a first differential input terminal and a second differential input terminal of the receiver, respectively.
It is an advantage of the present invention that, through a carefully designed control mechanism, the method, the common mode voltage re-biasing circuit, the receiver and the IC of the present invention can dynamically control common mode voltage re-biasing operations to correspond to the currently selected circuit configuration, and more particularly, utilizing the upper layer circuit such as a media access control (MAC) layer circuit to send the command according to the selected communications mode, to make the selected circuit configuration correspond to the selected communications mode, in order to guarantee the communications quality of each communications mode of the plurality of predetermined communications modes. In comparison with the related art, the method, the common mode voltage re-biasing circuit, the receiver and the IC of the present invention can achieve optimal performance of an electronic product without introducing side effects, or in a way that is less likely to introduce a side effect.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
As shown in
In this architecture, the control circuit 110 can generate at least one control signal such as the control signals CTRL1 and CTRL2 according to a command CMD, for controlling the common mode voltage re-biasing circuit 100 to operate in a selected circuit configuration. In addition, the multiple switchable common mode voltage re-biasing sub-circuits such as the switchable common mode voltage re-biasing sub-circuits 121 and 122 can select a predetermined circuit configuration from a first predetermined circuit configuration and a second predetermined circuit configuration according to the aforementioned at least one control signal such as the control signals CTRL1 and CTRL2 to be the selected circuit configuration to perform common mode voltage re-biasing operations corresponding to the selected circuit configuration, respectively.
For better comprehension, the first-type common mode voltage re-biasing sub-circuit 121A and the second-type common mode voltage re-biasing sub-circuit 121B in the switchable common mode voltage re-biasing sub-circuit 121 may have a first circuit architecture and a second circuit architecture, respectively, and the first-type common mode voltage re-biasing sub-circuit 122A and the second-type common mode voltage re-biasing sub-circuit 122B in the switchable common mode voltage re-biasing sub-circuit 122 may have another first circuit architecture that is the same as the first circuit architecture and another second circuit architecture that is the same as the second circuit architecture, respectively, where the second circuit architecture is different from the first circuit architecture. In addition, the control circuit 110 may selectively enable the first-type common mode voltage re-biasing sub-circuits 121A and 122A or enable the second-type common mode voltage re-biasing sub-circuits 121B and 122B through the aforementioned at least one control signal such as the control signals CTRL1 and CTRL2. For example, when enabling the first-type common mode voltage re-biasing sub-circuits 121A and 122A, the control circuit 110 may disable the second-type common mode voltage re-biasing sub-circuits 121B and 122B. For another example, when enabling the second-type common mode voltage re-biasing sub-circuits 121B and 122B, the control circuit 110 may disable the first-type common mode voltage re-biasing sub-circuits 121A and 122A.
The differential input signals DATA_P and DATA_N on the differential input terminals PAD_P and PAD_N may have a common mode voltage VCM1 (labeled “VCM1” on the two rightward paths from the differential input terminals PAD_P and PAD_N respectively for brevity), which is equal to the common mode voltage VCM1 at the node between the termination components 11 and 12, such as a predetermined common mode voltage input to this node. In this situation, the common mode voltage re-biasing circuit 100 can perform common mode voltage re-biasing on the differential input signals DATA_P and DATA_N, and more particularly, establish a common mode voltage VCM2 (labeled “VCM2” on the two rightward paths from the switchable common mode voltage re-biasing sub-circuits 121 and 122 for brevity), such as another predetermined common mode voltage, to replace the common mode voltage VCM1. During maintaining the common mode voltage VCM2, the common mode voltage re-biasing circuit 100 can dynamically control the common mode voltage re-biasing operations to correspond to the currently selected circuit configuration, to guarantee the communications quality of various communications modes.
For example, in various communications modes, the analog front-end circuit 10AF can correctly perform analog front-end processing, and more particularly, the differential amplifier 14 can correctly receive the adjusted differential input signals (e.g., adjusted versions of the differential input signals DATA_P and DATA_N, respectively on the two rightward paths from the switchable common mode voltage re-biasing sub-circuits 121 and 122 to the differential amplifier 14) that have been re-biased and have the common mode voltage VCM2, to obtain a series of logic values carried by the differential input signals DATA_P and DATA_N, and the data processing circuit 10DP can perform data processing on this series of logic values to allow the whole system comprising the receiver 10R to operate correctly. Therefore, the common mode voltage re-biasing circuit 100, the receiver 10R and the associated IC of the present invention can achieve the optimal performance of an electronic product without introducing side effects, or in a way that is less likely to introduce a side effect.
According to some embodiments, for a set of differential input signals received by the receiver 10R, such as the differential input signals DATA_P and DATA_N, a first frequency response of any switchable common mode voltage re-biasing sub-circuit among the first switchable common mode voltage re-biasing sub-circuit and the second switchable common mode voltage re-biasing sub-circuit when operating in the first predetermined circuit configuration and a second frequency response of the aforementioned any switchable common mode voltage re-biasing sub-circuit when operating in the second predetermined circuit configuration are different from each other. For example, for the set of differential input signals such as the differential input signals DATA_P and DATA_N, the first circuit architecture and the other first circuit architecture may play the role of low-pass filters, and the second circuit architecture and the other second circuit architecture can play the role of high-pass filters, but the invention is not limited thereto.
According to some embodiments, any of the first circuit architecture and the other first circuit architecture may comprise a first resistor and a second resistor, and any of the second circuit architecture and the other second circuit architecture may comprise a third resistor and a capacitor, but the invention is not limited thereto. In some embodiments, the first circuit architectures and/or the second circuit architectures may vary.
According to some embodiments, the plurality of predetermined communications modes may comprise communications modes of different generations (Gen) of the Peripheral Component Interconnect Express (PCIe) standard, such as the communications modes of PCIe 1st Generation (Gen 1/Gen1) to 5th Generation (Gen 5/Gen5), etc., where the transfer rates of PCIe Gen 1 to Gen 5 can be 2.5 Gigabits per seconds (Gbps), 5 Gbps, 8 Gbps, 16 Gbps and 32 Gbps, respectively, but the invention is not limited to this. In addition, the common mode voltage re-biasing circuit 100 can switch among different types of circuit architectures when the receiver 10R operates at the transfer rates of different generations. When the receiver 10R operates at a lower transfer rate such as 2.5 Gbps of PCIe Gen 1, the common mode voltage re-biasing circuit 100 can use the first circuit architectures with low-pass effects (e.g., the circuit architectures in the first predetermined circuit configuration shown in
In Step S10, the common mode voltage re-biasing circuit 100 can utilize the control circuit 110 to generate the aforementioned at least one control signal such as the control signals CTRL1 and CTRL2 according to the command CMD, for controlling the common mode voltage re-biasing circuit 100 to operate in a selected circuit configuration such as the selected circuit configuration above.
In Step S20, the common mode voltage re-biasing circuit 100 can utilize the multiple switchable common mode voltage re-biasing sub-circuits (e.g., the switchable common mode voltage re-biasing sub-circuits 121 and 122) of the common mode voltage re-biasing circuit 100 to select a predetermined circuit configuration such as the predetermined circuit configuration mentioned above from the first predetermined circuit configuration and the second predetermined circuit configuration according to the aforementioned at least one control signal such as the control signals CTRL1 and CTRL2 to be the selected circuit configuration to perform common mode voltage re-biasing operations corresponding to the selected circuit configuration, respectively.
In Step S21, the common mode voltage re-biasing circuit 100 can utilize the switchable common mode voltage re-biasing sub-circuit 121 to select the predetermined circuit configuration from the first predetermined circuit configuration and the second predetermined circuit configuration according to the aforementioned at least one control signal such as the control signals CTRL1 and CTRL2 to be the selected circuit configuration to perform first common mode voltage re-biasing operations corresponding to the selected circuit configuration.
In Step S22, the common mode voltage re-biasing circuit 100 can utilize the switchable common mode voltage re-biasing sub-circuit 122 to select the predetermined circuit configuration from the first predetermined circuit configuration and the second predetermined circuit configuration according to the aforementioned at least one control signal such as the control signals CTRL1 and CTRL2 to be the selected circuit configuration to perform second common mode voltage re-biasing operations corresponding to the selected circuit configuration.
During maintaining the common mode voltage VCM2, the common mode voltage re-biasing circuit 100 can dynamically control the common mode voltage re-biasing operations to correspond to the currently selected circuit configuration, to guarantee the communications quality of various communications modes. Therefore, the method, the common mode voltage re-biasing circuit 100, the receiver 10R and the IC 10 of the present invention can achieve the optimal performance of an electronic product without introducing side effects, or in a way that is less likely to introduce a side effect. For brevity, similar descriptions for this embodiment are not repeated in detail here.
For better comprehension, the method may be illustrated with the working flow shown in
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 111104284 | Feb 2022 | TW | national |
