Patent Application
20250133815
The present application is a non-provisional patent application claiming priority to European Patent Application No. 23205383.5, filed Oct. 24, 2023, the contents of which are hereby incorporated by reference.
The present disclosure refers to a method for processing a complementary field effect transistor (CFET) device.
In a CFET, different transistor structures, particularly NMOS and PMOS transistors, may be stacked on top of each other. Compared, for example, to a nanosheet device, which comprises NMOS and PMOS transistors arranged side by side with a spacing in between them. The stacking of the transistor structures enables increasing an effective channel width.
A step in the CFET fabrication is the deposition of a gate oxide layer, which is typically deposited around a nanosheet (NSH) stack that contains the NMOS and PMOS channels. However, fabricating this gate oxide to wrap around the NSH stack can be challenging.
Furthermore, subsequent fabrication steps (e.g., a full gate etching step) can damage the gate oxide and the underlying NSH stack, which can reduce the CFET performance. This damaging of the NSH stack is sometimes referred to as “NSH erosion”. NSH erosion is typically increased when the gate oxide layer on top of the NSH stack is relatively thin, because a thin gate oxide offers less protection to the NSH stack underneath.
Thus, it is an objective to provide an improved method for processing a CFET device. In particular, the above-mentioned disadvantages should be avoided.
The objective is achieved by the embodiments provided in the enclosed independent claims and disclosure herein. Implementations of the embodiments of the disclosure are further defined in the dependent claims.
A first aspect of this disclosure provides a method for processing a complementary field effect transistor (CFET) device. The method comprises the steps of forming at least one fin structure on a substrate, wherein the at least one fin structure comprises a horizontal top surface and two vertically oriented side surfaces between the top surface and the substrate, and wherein the at least one fin structure comprises a first layer stack and a second layer stack above the first layer stack, and forming a gate dielectric layer with a non-uniform layer thickness around the at least one fin structure, wherein the layer thickness of the gate dielectric layer which is arranged on the top surface of the at least one fin structure is larger than the layer thickness of the gate dielectric layer which is arranged on the side surfaces of the at least one fin structure.
This provides that the fin structure can be efficiently protected from damage during subsequent fabrication steps. This is due to the increased layer thickness of the gate dielectric on the top surface of the fin structure, where subsequent fabrication steps (e.g., a full gate etch) would cause damage. In particular, so-called NSH erosion of the layers within the fin structure can be reduced.
The thicker gate dielectric layer on the top surface can serve as a protective layer for the fin structure, while the layer thickness of the gate dielectric layer on the side surfaces of the fin structure can be reduced to a level which allows accessing and/or performing further processing steps in the space between two adjacent fin structures (e.g., a gate oxide breakthrough step).
The top surface of the fin structure can be an area on the fin structure which wraps around a tip of the fin structure, wherein most or (e.g., substantially) all of the top surface is facing away from the substrate. For instance, the top surface of the fin structure is tapered (i.e., not fully flat). The vertical side surfaces can be surfaces of the side walls of the fin structure.
The gate dielectric layer can be a gate oxide (Gox) layer.
Hereby, processing the CFET device may refer to fabricating or manufacturing the CFET device.
In an embodiment, the layer thickness of the gate dielectric layer which is arranged on the top surface of the at least one fin structure is between 1.5 and 3 times larger than the layer thickness of the gate dielectric layer which is arranged on the side surfaces of the at least one fin structure.
This achieves that the gate dielectric layer on top of the fin structure can serve as an additional protection layer to prevent NSH erosion.
In an embodiment, the gate dielectric layer is a silicon dioxide (SiO2) layer.
In an embodiment, the gate dielectric layer is deposited on the at least one fin structure by means of a layer deposition technique, such as plasma enhanced atomic layer deposition (PEALD) or pulsed chemical vapor deposition (CVD).
In an embodiment, the gate dielectric layer is thereby formed on the top surface of the at least one fin structure with a different film quality than on the side surfaces of the at least one fin structure.
Hereby, different film quality may refer to a different (e.g., higher) film density related with and/or dielectric stoichiometry and composition of the gate dielectric layer at the top surface of the fin structures compared to the side surfaces. This can result in a higher film stability (e.g., chemical stability) of the gate dielectric layer on the top surface compared to the gate dielectric layer on the side surfaces.
In particular, a non-conformal/non-uniform deposition of the gate dielectric layer can be realized by a single deposition step, e.g., in contrast to a conformal/uniform deposition with additional plasma treatments. For instance, the dielectric layer can be deposited on the top surface of the fin structure with a higher deposition rate than on the side surfaces during the same deposition process.
In an embodiment, after deposition, the layer thickness of the gate dielectric layer around the at least one fin structure is reduced by means of an etching step.
This etching step can generate and/or enhance the difference in layer thickness between the gate dielectric layer on the top surface and the side surfaces of the fin structure. For instance, the etching step can be a wet etching with a hydrofluoric acid (HF) solution.
In an embodiment the etching step has a higher etching rate on the gate dielectric layer which is arranged on the side surfaces of the at least one fin structure than on the gate dielectric layer which is arranged on the top surface of the at least one fin structure.
This can be due to the high film quality and/or stability of the gate dielectric layer on the top surface compared to the gate dielectric layer on the side surfaces of the fin structure.
Thus, a step coverage control with a post-wet treat can result in a thickness modulation of the gate dielectric layer around the 3D topography of the fin structure and/or to non-conformal depositions for tight pitch fin structures, e.g., for CFET FEOL integration. Hereby, the non-conformal deposition may refer to a loading of the fin structure with a thickness difference between the top surface (thicker gate dielectric) and the side walls (thinner gate dielectric).
In an embodiment, the method comprises the further step of selectively adapting, in particular densifying, the gate dielectric layer which is arranged on the top surface of the at least one fin structure.
In this way, the film quality and/or stability of the gate dielectric layer on the top surface can be further enhanced.
In an embodiment, the step of selectively adapting the gate dielectric layer is carried out directly after a deposition of the gate dielectric layer or directly prior to a full gate etching step.
In an embodiment, the selective adaptation of the gate dielectric layer is carried out by any one of the following techniques: plasma treatment, UV treatment or annealing.
In an embodiment, an array of two or more fin structures is generated simultaneously.
In an embodiment, the method comprises the further step of forming at least one gate structure on or around the at least one fin structure.
The gate structure can be a fin-like structure which is arranged perpendicular to the fin structure. The gate structure can be a dummy gate structure. The dummy gate structure can be replaced in a later step by a replacement metal gate structure.
In an embodiment, the first layer stack comprises at least one channel layer of a first transistor structure of the CFET device, and the second layer stack comprises at least one channel layer of a second transistor structure of the CFET device.
The first (or bottom) transistor structure can be arranged in a first tier (or level) and the second (or top) transistor structure can be arranged in a second tier (or level) of the CFET device, wherein the second tier is arranged above the first tier. This may result in stacked transistor structures of the CFET device. The CFET device may comprise further transistor structures or other elements, which could respectively be directly above or beneath the first and second transistor structure.
For instance, the first transistor structure and the second transistor structure can form a CFET cell. The CFET device can comprise one or more CFET cells or parts thereof.
Notably, in this disclosure, the terms “below” and “above”, “bottom” and “top”, or similar terms are to be interpreted relative to each other. In particular, these terms describe opposite sides of the CFET device, or opposite side of any element of the CFET device. The terms may describe a relationship of elements (e.g., transistor structures, signal routing lines, power rails, etc.) of the CFET device along the direction of stacking of the tiers (or levels) of the CFET device. The stacking direction may thus align with the arrangement of the two tiers (or even more than two tiers) of the CFET device. That is, the two or more tiers (or levels), which are arranged above each other, are arranged one after the other along a certain direction (the stacking direction).
A transistor structure in this disclosure may be or may comprise a transistor, for example a field effect transistor (FET), or may be or may comprise a more complex semiconductor-based structure, which functions like a transistor. For instance, the semiconductor-based structure may be a nanosheet structure, a fin structure, or a forksheet structure, for example, provided with a gate partly wrapping around or fully wrapping around channel portions. The latter may be for instance a gate-all-around structure.
The transistor structures of the CFET device of the first aspect may be NMOS and PMOS transistor structures. For instance, the first transistor structure may be an NMOS transistor structure and the second transistor structure a PMOS transistor structure, or vice versa.
In an embodiment, the method comprises the further steps of forming a first source and/or drain structure which is in electrical contact with the first layer stack of the at least one fin structure, and forming a second source and/or drain structure which is in electrical contact with the second layer stack of the at least one fin structure.
For instance, the source and/or drain structures are formed by an epitaxial growth process.
A second aspect of this disclosure provides a CFET device obtainable by the method according to the first aspect of this disclosure.
Such a CFET device produced with the method of the first aspect of the disclosure shows clear “fingerprints” of that method. For instance, an electronic microscope image of a cross-section of the CFET device can reveal the different layer thicknesses of the gate dielectric layer on the top surface and the side surfaces of the fin structure.
The above, as well as additional, features will be better understood through the following illustrative and non-limiting detailed description of example embodiments, with reference to the appended drawings.
FIGS. 2A1, 2A2, 2B1, and 2B2 show a step of a method for processing a CFET device according to an example embodiment; and
FIGS. 3A1, 3A2, 3B1, and 3B2 show a step of a method for processing a CFET device according to an example embodiment.
All the figures are schematic, not necessarily to scale, and generally only show parts which are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested.
Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. That which is encompassed by the claims may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example. Furthermore, like numbers refer to the same or similar elements or components throughout.
In the example shown in
In a first step, shown in
The at least one fin structure 23 comprises a first layer stack 23a and a second layer stack 23b above the first layer stack 23a.
The first layer stack 23a may comprise at least one channel 11a of a first transistor structure of the CFET device and the second layer stack 23b may comprise at least one channel 12a of a second transistor structure of the CFET device. For instance, the first transistor structure is a bottom transistor structure and the second transistor structure is a top transistor structure of the CFET device. The bottom transistor structure can be a NMOS and the top transistor structure can be a PMOS, or vice versa.
The first and second layer stack 23a, 23b can be arranged directly on top of each other. Each layer stack 23a, 23b can comprise a plurality of alternating layers, comprising at least one channel layer (e.g., a Si layer) and at least one dielectric layer. For instance, each layer stack 23a, 23b can comprise alternating Si and SiGe layers. A top layer of the fin structure 23 can be a Si3N4 layer. A dielectric separation layer stack (e.g., middle dielectric isolation, MDI) can be arranged between the first and second layer stack 23a, 23b. For instance, the separation layer stack can comprise a SiGe layer (with high % Ge) which was originally a part of the Si/SiGe layer stack 23a, 23b and is converted to a dielectric in a subsequent step. However, the dielectric separation layer stack can also be a part of the first or the second layer stack 23a, 23b, e.g., in case of embedded MDI.
The fin structure 23 can be formed on a substrate 14 by active nanosheet patterning, e.g., by patterning of a nanosheet stack on the substrate 14. The nanosheet stack can comprise the layer stacks 23a, 23b and the dielectric separation layer stack.
As shown in
The gate dielectric layer 41 can be a gate oxide layer, such as a silicon dioxide (SiO2) layer.
The gate dielectric layer 41 can be deposited around the fin structure 23 in a first step, shown in
Subsequently, the layer thickness of the gate dielectric layer 41 can be reduced by means of an etching step, as shown in
For example, the layer thickness of the gate dielectric layer 41 which is arranged on the top surface of the at least one fin structure 23 is between 1.5 and 3 times larger than the layer thickness of the gate dielectric layer 41 which is arranged on the side surfaces of the at least one fin structure 23.
This non-conformal thickness of the gate dielectric layer 41 can be included in different integration schemes and modules. For instance, the thicker dielectric layer 41 on the top surface of the fin structure 23 can serve as a protective layer during subsequent processing steps. In this way, for instance, NSH erosion effects can be reduced. Furthermore, a reduced layer thickness on the side surfaces of the fin structure 23 can provide more room for downstream integration applications between the adjacent fins, in particular when using high aspect ratio fin structures 23 with tight spacing between the lines.
The gate dielectric layer 41 could be directly deposited as a non-conformal layer, e.g., with a higher layer thickness on the top surface compared to the side surfaces of the fin structure 23. This non-conformity can then be further enhanced by means of the etching step (shown in
Alternatively, the gate dielectric layer 41 can be deposited as a uniform (conformal) layer with a (mostly) uniform layer thickness and the non-conformity can be generated by means of the etching step (shown in
The etching step can be a wet etching with hydrofluoric acid (HF). Thereby, a concentration of the HF and/or an etching time can be adjusted to achieve target layer thicknesses on the top and side surfaces.
For instance, during deposition (shown in
This increased film quality (e.g., density, stability) of the gate dielectric layer 41 on the top surface can cause a lower etching rate on this portion of the gate dielectric layer 41 during the etching step (
Furthermore, the concentration of the etchant and/or the etching time can be adapted to achieve target layer thicknesses on the top and side surfaces. In an example, the etching rate of the gate dielectric layer 41 with an HF solution can be 2-10 nm/min at the top surface and 3-30 nm/min at the side surfaces (depending on the HF concentration). The resulting gate dielectric layer can have a thickness of >5 nm on the top surface and <4 nm on the side surfaces.
Thus, by using conformal or non-conformal gate dielectric films or layers 41 deposited, for example, by PEALD and a suitable wet treat (e.g., with HF), the thickness of the gate dielectric layer 41 can be tuned at the side walls and at the top of the fin structure 23. This tuning can be supported by varied film qualities on the top and the side surfaces of the fin structure 23 possibly obtained in the deposited state.
The gate dielectric layer 41 may further be formed on the substrate 14 in an area between two adjacent fin structures 23. The layer thickness of the gate dielectric layer 41 on the substrate 14 could also be larger than the layer thickness on the respective side surfaces of the fin structures 23. The extent of this effect might depend on the spacing and aspect ratio of the fin structures 23.
As shown in
Furthermore, as shown in
In particular, the source or drain terminals or structures 11b, 12b (also referred to as source or drain terminals 11b, 12b) can be arranged to electrically contact the channel(s) 11a, 12a of the first layer stack 23a or the second layer stack 23b, respectively. For instance, the source or drain terminals 11b, 12b can be formed by means of an epitaxial growth process on or around the channel(s) 11a, 12a.
Prior to forming the source and/or drain structures 11b, 12b, the fin structure 23 can be partially removed to expose the channels 11a, 12a.
The source and/or drain terminals 11b, 12b are indicated by dashed boxes in
In further steps of the method, which are not shown in
Furthermore, power rails (e.g., a VDD and a VSS power rail) can be formed that contact the first transistor structure respectively the second transistor structure. In addition, a set of signal routing lines of the CFET device can be formed in a metal layer above the transistor structures, and can be connected to the first and the second transistor structure.
The method shown in
FIGS. 2A1, 2A2, 2B1, and 2B2 show a further, optional step of the method for fabricating the CFET device, according to an example embodiment. The step is a selective adaption of the gate dielectric layer 41 which is arranged on the top surface of the at least one fin structure 23.
This step can be carried out after formation of the gate dielectric layer 41, e.g., directly after the layer deposition shown in
The drawing in FIG. 2A1 shows a cross-section view of the fin structure 23 through an y-z plane (along a fin extension direction/channel direction) and the drawing in FIG. 2A2 shows a cross-section view of the fin structure 23 through a x-z plane (perpendicular to a fin extension direction/channel direction) after the gate dielectric layer deposition. Thereby, the internal first and second layer stack 23a, 23b can be seen.
The substrate 14 between the fin structures 23 can be covered by a shallow trench isolation (STI) layer 42.
The adaption of the gate dielectric layer 41 is indicated by arrows in the drawings of FIG. 2B1 and 2B2. For instance, the adaption can be a densification of the layer 41. This adaption (e.g., densification) being “selective” means that only a part of the gate dielectric layer 41, namely the part that is arranged on the top surface of the fin structure 23, is treated.
This adaptation can further enhance the stability of the gate dielectric layer 41 on the top surface of the fin structure 23. Consequently, the gate dielectric layer 41 on the top surface can be more robust during subsequent fabrication steps. For instance, a NSH erosion during a full gate etching (FGE) soft landing attack can be further reduced.
The partial removal of dummy gate material at the FGE can be done by patterning the gate material, comprising (1) depositing and patterning a hard mask layer above the dummy gate using single-or multiple-patterning techniques), and (2) thereafter the dummy gate layer may be etched, e.g., using a dummy gate hard mask as an etch mask, using a dry (plasma) etch. When dummy material is etched down to the bottom of the fins, the risk of also eroding the top surface of the gate oxide such that the underlying nanosheets of the channels are attacked is avoided by the thicker (and adapted) top part of the gate oxide (gate dielectric layer 41). In later steps, this remaining gate oxide directly below the dummy gate structures can be completely removed and replaced by a final gate dielectric (e.g., HfO2, during a replacement metal gate step).
The selective adaptation of the gate dielectric layer 41 can be carried out using one or more of the following techniques a plasma treatment, a UV treatment or an annealing of the gate dielectric layer 41.
FIGS. 3A1, 3A2, 3B1, and 3B2 show further views of a fin structure 23 during a later stage of the fabrication process, namely after formation of the dummy gate structure 32, according to an example embodiment.
Thereby, FIG. 3B1 and 3B2 show the selective adaption of the gate dielectric layer 41 being carried out after the dummy gate formation but prior to the full gate etch. The treatment (e.g., densification) of the gate dielectric layer 41 on the top surface of the fin structure 23 is indicated by arrows in the right drawing.
The (dummy) gate structure 32 can be formed from aSi (amorphous silicon). The aSi material can comprise a silicon nitride (Si3N4) and silicon oxide (SiOx) layer on top.
In the claims as well as in the description of this disclosure, the word “comprising” does not exclude other elements or steps and the indefinite article “a” or “an” does not exclude a plurality. A single element may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in a beneficial implementation.
While some embodiments have been illustrated and described in detail in the appended drawings and the foregoing description, such illustration and description are to be considered illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be construed as limiting the scope.
| Number | Date | Country | Kind |
|---|---|---|---|
| 23205383.5 | Oct 2023 | EP | regional |
