Claims
- 1. A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element comprising:
- converting said hardware independent user description into a graph structure in a computer memory wherein said hardware independent user desctiption includes first instructions of a form: ##EQU1## wherein signal COND is a condition; and signal Q is a logic signal that is assigned a logic value of signal D; and
- generating a latch having an input data line, a latch gate line, and an output line using information, generated from said first instructions, in said graph structure;
- wherein said signal D is on said input data line;
- said signal COND on said latch gate line; and
- said logic signal Q is on said output line.
- 2. A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element as in claim 1 wherein said hardware independent user description includes second instructions of a form: ##EQU2## wherein signal positive.sub.-- edge(CLOCK) is a condition representing a positive edge of a clock signal CLOCK; and
- signal B is a logic signal that is assigned a logic value of signal C; and
- said method further comprises:
- generating a D-type flip-flop having an input data line, a clock line, and an output line using information, generated from said second instructions, in said graph structure;
- wherein said signal C is on said input data line;
- said signal positive.sub.-- edge(CLOCK) is on said clock line; and
- said logic signal B is on said output line.
- 3. A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element as in claim 2 wherein said hardware independent user description includes third instructions of a form: ##EQU3## wherein signal positive.sub.-- edge (CLOCK1) is a condition representing a positive edge of a clock signal CLOCK1;
- signal A is a logic signal;
- signal "Z" is a high impedance signal;
- signal E is a non-constant logic signal; and
- said method further comprises:
- generating using information, generated from said third instructions, in said graph structure a second D-type flip-flop having an input data line, a clock line, and an output line;
- wherein said signal E is on said input data line of said second D-type flip-flop; and
- said signal positive.sub.-- edge(CLOCK1) is on said clock line of said second D-type flip-flop; and
- generating using information in said graph structure generated from said third instructions, a three state element having a data input line, an enable line, and an output line;
- wherein said three state element data input line is connected to output line of said second D-type flip-flop;
- said three state element enable line is connected to said third D-type flip-flop output line through an inverter; and
- said logic signal A is on said output line of said three-state element.
- 4. A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element as in claim 3 wherein said hardware independent user description includes fourth instructions of a form: ##EQU4## wherein signal positive.sub.-- edge(CLOCK4) is a condition representing a positive edge of a clock signal CLOCK4;
- signal A1 is a logic signal;
- signal b+c is a logic OR of non-constant logic signals b and c; and
- said method further comprises:
- generating using information, generated from said fourth instructions, in said graph structure a fourth D-type flip-flop having an input data line, a clock line, and an output line;
- wherein said signal positive.sub.-- edge(CLOCK4) is on said clock line of said fourth D-type flip-flop; and
- said signal A1 is on said output line of said fourth D-type flip-flop;
- generating using information, generated from said fourth instructions, in said graph structure a multiplexer having:
- a first input terminal connected to said output line of said fourth D-type flip-flop;
- a second input terminal connected to an output terminal of an OR gate wherein a first input terminal of said OR gate is connected to receive said signal b and a second input terminal of said OR gate is connected to receive said signal c;
- an input signal select terminal connected to said condition signal COND4; and
- an output terminal connected to said input line of said fourth D-type flip-flop.
- 5. A method for converting a hardwware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element as in claim 1 wherein said hardware independent user description includes second instructions of a form: ##EQU5## wherein signal positive.sub.-- edge(CLOCK1) is a condition representing a positive edge of a clock signal CLOCK1;
- signal A is a logic signal;
- signal "Z" is a high impedance signal; and
- signal E is a non-constant logic signal; and
- said method further comprises:
- generating using information, generated from said second instructions, in said graph structure a first D-type flip-flop having an input data line, a clock line, and an output line;
- wherein said signal E is on said input data line of said first D-type flip-flop; and
- said signal positive.sub.-- edge(CLOCK1) is on said clock line of said first D-type flip-flop;
- generating using information, generated from said second instructions, in said graph structure a first D-type flip-flop having an input data line, a clock line, and an output line;
- wherein said signal COND is on said input data line of said second D-type flip-flop;
- said signal positive.sub.-- edge(CLOCK1) is on said clock line of said second D-type flip-flop;
- generating, using information in said graph structure generated from said second instructions, a three state element having a data input line, an enable line, and an output line;
- wherein said three state element data input line is connected to output line of said first D-type flip-flop;
- said three state element enable line is connected to said second D-type flip-flop output line through an inverter; and
- said logic signal A is on said output line of said three-state element.
- 6. A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element as in claim 1 wherein said hardware independent user description includes second instructions of a form: ##EQU6## wherein signal positive.sub.-- edge(CLOCK4) is a condition representing a positive edge of a clock signal CLOCK4;
- signal A1 is a logic signal;
- signal b+c is a logic OR of non-constant logic signals b and c and
- said method further comprises:
- generating using information, generated from said second instructions, in said graph structure a D-type flip-flop having an input data line, a clock line, and an output line;
- wherein said signal positive.sub.-- edge(CLOCK4) is on said clock line of said D-type flip-flop; and
- said signal A1 is on said output line of said D-type flip-flop;
- generating using information, generated from said second instructions, in said graph structure a multiplexer having:
- a first terminal connected to said output line of said D-type flip-flop;
- a second input terminal connected of an output terminal of an OR gate wherein a first input terminal of said OR gate is connected said signal b and a second input terminal of said OR gate is connected to said signal c;
- an input signal select terminal connected to said condition signal COND4; and
- an output terminal connected to said input line of said D-type flip-flop.
- 7. A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element comprising:
- converting said hardware independent user description into a graph structure in a computer memory wherein said hardware independent user description includes instructions of a form: ##EQU7## wherein signal positive.sub.-- edge(CLOCK) is a condition representing a positive edge of a clock signal CLOCK; and
- signal B is a logic signal that is assigned a logic value of signal C; and
- generating a D-type flip-flop having an input data line, a clock line, and an output line using information, generated from said instructions, in said graph structure;
- wherein said signal C is on said input data line;
- said signal positive edge(CLOCK) is on said clock line; and
- said logic signal B is on said output line.
- 8. A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element comprising:
- converting said hardware independent user description into a graph structure in a computer memory wherein said hardware independent user description includes instructions of a form: ##EQU8## wherein signal positive.sub.-- edge(CLOCK1) is a condition representing a positive edge of a clock signal CLOCK1;
- signal A is a logic signal;
- signal "Z" is a high impedance signal; and
- signal E is a non-constant logic signal; and
- generating using information, generated from said instructions, in said graph structure a first D-type flip-flop having an input data line, a clock line, and an output line;
- wherein said signal E is on said input data line of said first D-type flip-flop; and
- said signal positive.sub.-- edge(CLOCK1) is on said clock line of said first D-type flip-flop;
- generating using information, generated from said instructions, in said graph structure a second D-type flip-flop having an input data line, a clock line, and an output line;
- wherein said signal COND is on said input data line of said second D-type flip-flop;
- said signal positive.sub.-- edge(CLOCK1) is on said clock line of said second D-type flip-flop; and
- generating, using information in said graph structure generated from said instructions, a three state element having a data input line, an enable line, and an output line;
- wherein said three state element data input line is connected to output line of said first D-type flip-flop;
- said three state element enable line is connected to said second D-type flip-flop output line through an inverter; and
- said logic signal A is on said output line of said three-state element.
- 9. A method for converting a hardware independent user description containing flow control statements including an IF statement and directive statements into a logic hardware element comprising:
- converting said hardware independent user description into a graph structure in a computer memory wherein said hardware independent user description includes instructions of a form: ##EQU9## wherein signal positive.sub.-- edge(CLOCK4) is a condition representing a positive edge of a clock signal CLOCK4;
- signal A1 is a logic signal;
- signal b+c is a logic OR of non-constant logic signals b and c; and
- generating using information, generated from said fourth instructions, in said graph structure a D-type flip-flop having an input data line, a clock line, and an output line;
- wherein said signal positive.sub.-- edge(CLOCK4) is on said clock line of said D-type flip-flop; and
- said signal A1 is on said output line of said D-type flip-flop; and
- generating using information, generated from said instructions, in said graph structure a multiplexer having:
- a first terminal connected to said output line of said D-type flip-flop;
- a second input terminal connected of an output terminal of an OR gate wherein a first input terminal of said OR gate is connected said signal b and a second input terminal of said OR gate is connected to said signal c;
- an input signal select terminal connected to said condition signal COND4; and
- an output terminal connected to said input line of said D-type flip-flop.
RELATED APPLICATIONS
This application is a continuation of commonly assigned U.S. patent application Ser. No. 08/472,026, entitled "A METHOD FOR PROCESSING A HARDWARE INDEPENDENT USER DESCRIPTION TO GENERATE LOGIC CIRCUIT ELEMENTS INCLUDING FLIP-FLOPS, LATCHES, AND THREE-STATE BUFFERS AND COMBINATIONS THEREOF" of Brent L. Gregory and Russell B. Segal, filed on Jun. 6, 1995, now U.S. Pat. No. 5,661,661, which in turn was a continuation of commonly assigned U.S. patent application Ser. No. 07/632,439 entitled "METHOD AND APPARATUS FOR SYNTHESIZING HDL DESCRIPTIONS WITH CONDITIONAL ASSIGNMENTS" of Brent L. Gregory and Russell B. Segal, filed on Dec. 21, 1990, now abandoned.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
5661661 |
Gregory et al. |
Aug 1997 |
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Continuations (2)
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Number |
Date |
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Parent |
472026 |
Jun 1995 |
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Parent |
632439 |
Dec 1990 |
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