BRIEF DESCRIPTION OF THE DRAWINGS
These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:
FIG. 1 is a schematic circuit diagram of a lifting scheme in accordance with prior art;
FIG. 2 is an analytic diagram of the algorithm of the lifting scheme in accordance with prior art, when the lifting scheme is used to accomplish forward 9/7 DWT;
FIG. 3 is a schematic circuit diagram of a pipeline lifting scheme in accordance with prior art;
FIG. 4 is a schematic circuit diagram of a Flipping scheme in accordance with prior art;
FIG. 5
a is a schematic circuit diagram of a one-level two-dimensional DWT in accordance with prior art;
FIG. 5
b is a schematic system diagram of the one-level two-dimensional DWT in FIG. 5b;
FIG. 6 is a schematic data processing flow diagram of the one-level two-dimensional DWT in accordance with prior art;
FIG. 7 is a flow chart of a DWT method in accordance with the present invention;
FIG. 8
a is an analytic diagram of the DWT method in accordance with the present invention;
FIG. 8
b is an analytic diagram of the DWT method in accordance with the present invention;
FIG. 8
c is an analytic diagram of the DWT method in accordance with the present invention;
FIG. 8
d is an analytic diagram of the DWT method in accordance with the present invention;
FIG. 9 is a circuit diagram of the DWT method in accordance with the present invention;
FIG. 10 is a schematic diagram of a scanning method for low area DWT;
FIG. 11
a is a schematic system diagram of a low area 2-D DWT in accordance with the present invention;
FIG. 11
b is a circuit diagram of the low area 2-D DWT in FIG. 1a; and
FIG. 12 is a schematic flow diagram of processing 2-D data in accordance with the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
Refer to FIG. 7. FIG. 7 is a flow diagram in accordance with the present invention. The embodiment of the present invention takes a forward 9/7 discrete wavelet transform module complying with the JPEG 2000 compression standard for example. The input data, such as an image, is transformed by the DWT module, which generates the output data. The output data is stored in an appropriate circuit unit.
In using the lifting scheme to complete 9/7 DWT, the equation (1) Y(2n+1)←Xext(2n+1)+α×[Xext(2n)+Xext(2n+2)] as described in the conventional lifting scheme can be rewritten as,
Y(2n+1)←α×Xext(2n)+Xext(2n+1)+α×Xext(2n+2) (7)
The method in accordance with the present invention is to use the common product of sequel terms in the equation (7) to eliminate the circuit being idle. The circuit needs to process data computation including addition and multiplication at each time term, where each time term represents a time point along the time axis so that the flow processing performance is efficiently improved. The DWT circuit computes simultaneously the data at both T(2n) and T(2n+1) time terms along the time axis. If two records of Xext(2n) and Xext(2n+1) can be simultaneously processed, the data computation time is saved. Meanwhile, the computation flow of the DWT algorithm will not increase multiplication times.
Taking the algorithm for example, if n=0 and n=1 are respectively loaded into the equation (7), then the equation (8) and (9) can be obtained as,
Y(1)←α×Xext(0)+Xext(1)+α×Xext(2) (8)
Y(3)←α×Xext(2)+Xext(3)+α×Xext(4) (9)
wherein, the product of α×Xext(2), i.e. the product of α×Xext(2n) can be the common product for the sequel equations (8) and (9).
Refer to FIG. 8a. FIG. 8a shows the first step of the algorithm generally uses the T(2n+1) time terms of the two adders and the T(2n) time terms of the one multiplier by means of the common product of the sequel equations, where the time terms of T(2n+1) are the odd time points along the time axis, the time terms of T(2n) are the even time points along the time axis, and n is zero or and an integer.
Refer to FIG. 8b. FIG. 8b shows the second step of the algorithm generally uses the T(2n+1) time terms of one adder and the T(2n) time terms of the one multiplier and one adder to process hardware timing. The hardware timing of the multiplier is the same between the first and the second steps.
Refer to FIG. 8c. FIG. 8c shows the third step of the algorithm can do the same modification. The third step generally uses the T(2n) time terms of two adders and the T(2n+1) time terms of one multiplier. The hardware timing of the computational components in the third step is staggered with respect to the first and the second steps. For example, in the odd time point T(n+11) along the time axis, the first stage uses two adders, while the second stage uses simultaneously one adder and the third stage uses simultaneously the multiplier for r coefficient. In the even time point T(n+12) along the time axis, the first stage uses the multiplier for α coefficient, while the second stage uses simultaneously one adder and the multiplier for β coefficient, and the third stage uses simultaneously two adders.
Therefore, the multiplier can be commonly used for different coefficients in the first stage and third stage by exchanging its coefficients with setting the even time points for the coefficient α and the odd time points for the coefficient γ.
Refer to FIG. 8d. FIG. 8d shows the fourth step of the algorithm. It generally uses the T(2n) time terms of one adder, and the T(2n+1) time terms of the one multiplier and one adder. The hardware timing of the fourth step is staggered with respect to the first and the second steps. For example, in the even time point T(n+16) along the time axis, the first stage uses the multiplier for coefficient α, while the second stage uses simultaneously the multiplier for coefficient β and one adder, the third stage uses simultaneously two adders and the fourth stage uses simultaneously one adder. In the odd time point T(n+17), the first stage uses two adders, while the stage use simultaneously one adder, the third stage uses simultaneously the multiplier for coefficient γ, and the fourth stage uses simultaneously the multiplier for coefficient δ and one adder.
Therefore, the first multiplier can be commonly used for first stage and third stage by exchanging its coefficients with setting the even time points for the coefficient α and the odd time points for the coefficient γ. Likewise, the second multiplier can be commonly used for second stage and fourth stage by exchanging its coefficients with setting the even time points for the coefficient β and the odd time points for the coefficient δ. Thus, the computation results of the aforesaid steps are multiplied by corresponding coefficients (i.e. K or 1/K) to obtain respectively detailed coefficients and smooth coefficients.
Consequently, this embodiment only needs two multipliers and four adders to accomplish the 1-D DWT algorithm with a control circuit to exchange the product of the multipliers. The latency of the critical path becomes only the computation time of one multiplier. Refer to FIG. 9. FIG. 9 shows, the digital image processing apparatus 10 in accordance with the present invention to compute the 1-D forward 9/7 DWT. The digital image processing apparatus 10 in FIG. 9 comprises a first multiplier 100, a second multiplier 103, a first adder 101, a second adder 102, a third adder 104 and a fourth adder 105. The first and the second adders 101 and 102 use the time terms of T(2n+1) for the hardware processing time, while the first multiplier 100 uses the time terms of T (2n) for the hardware processing time. The third and the fourth adders 104, 105 use the time terms of T(2n) for the hardware processing time, while the second multiplier 103 uses the time terms of T (2n+1) for the hardware processing time. “n” is an integer, the time terms of T(2n+1) are odd time points along the time axis, and the time terms of T(2n) are even time points along the time axis. Besides, the present invention can be used to accomplish not only the forward 9/7 DWT, but also the forward 5/3 DWT.
With reference to FIG. 10, the preferred embodiment adopts non-overlapped stripe-based scanning method for the 2-D DWT circuit. The scanning method starts to scan the first row, and waits for the completion of the inputting of first row data. Then, the scanning method starts to scan a group of two rows of non-overlapped stripe-based scanning inputs.
Refer to FIG. 11a and FIG. 11b. FIG. 11a and FIG. 11b illustrate a schematic diagram of the 2-D DWT in accordance with the present invention. The input data sequence is processed by a column 1-D DWT unit 200 in advance to perform the column process. The letter M in blocks in the FIG. 11a represents a number of adopted multipliers, and the letter A in blocks in the FIG. 11a represents a number of adopted adders. When the computation of the 1-D column DWT has been completed, the analytic outputs including low pass output and high pass output are respectively sent to a low pass row DWT module 201 and a high pass DWT module 202.
There is no different if row processing or column processing is being taken in advance for the image for dealing with the 2-D DWT. However, a transposing buffer is required to temporally store the transformed data of the image when one direction of the image has been completed by the 1-D DWT, and the transformed data are transformed to another direction of the image. The transposing buffer for the transformed data needs 1.5N words in size, where N is the length of the image. Using the non-overlapped stripe-based scanning method can eliminate the required transposing buffer used in the 2-D DWT circuit.
With further reference to FIG. 12, two pieces of sequel image data 300,301 of the j-th column are inputted. Then, two pieces of sequel image data 302 and 303 of the j+1th column in the same row are inputted. Therefore, the outputs of the column DWT module 200 generates the high pass output 304 at the position [i+1, j] in advance, and then generates the low pass output 305 at position [i, j], the high pass output 306 at position [i+1, j+1] and the low pass output 307 at position [i, j+1] in sequence. Only high pass outputs or low pass outputs can be recognized at every period of two pulses and generate the transformed data in the same row but different columns. Consequently, there is no need to have a transposing buffer to temporally store the data transmitted to the row DWT modules 201 and 202. Not having a transposing buffer results in reducing the circuit area into a smaller size.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Patent Application
20080056372
