Patent Application
20200083385
The present application relates to the technical field of display, and particularly relates to a method for processing a display panel and a display panel.
At present, each pixel of a TFT-LCD (Thin Film Transistor-Liquid Crystal Display) is mainly controlled by one TFT (Thin Film Transistor) switch, and the gates of the TFT switches are connected together to form a gate line, and the source layers of the TFT switches are connected together to form a signal line. When a voltage is applied to a gate layer G (Gate) of the TFT, the TFT may be brought into a conducting state, and the display data is able to pass through the signal line and the conducting TFT to arrive a drain layer D (Drain) of the TFT, thus forming an electric field on the pixel and charging the liquid crystal to achieve a display effect.
Usually, it is better when the on-state current of the TFT of an ideal TFT-LCD display is larger, and the off-state current of the TFT of an ideal TFT-LCD display is smaller. In order to prevent the leakage current from increasing due to backlight illumination, existing TFT-LCDs adopt a bottom gate structure to prevent an increase in the leakage current caused by the backlight directly illuminating the channel. However, the capacitance of the gate and the source/drain layer of the bottom gate structure is relatively large, an excessive parasitic capacitance not only causes erroneous writing of the pixel voltage, but also increases the drift of the threshold voltage Vth (Threshold voltage), and severe Vth drift will lead to the appearance of afterimages.
The purpose of the present application is to provide a method for processing a display panel, and is aimed at solving the problem how to decrease the parasitic capacitance disposed between two sides of the gate layer.
The present application is implemented in a way that, a method for processing a display panel, which includes the following steps of:
preparing a substrate;
forming a first metal layer on the substrate;
forming a light shielding layer attached to the substrate at a lateral side of the first metal layer;
forming an insulation layer on the first metal layer, the light shielding layer and the substrate, wherein the first metal layer and the light shielding layer are each disposed between the insulation layer and the substrate;
forming a semiconductor layer on the insulation layer;
forming a second metal layer on the semiconductor layer, wherein the semiconductor layer is disposed between the insulation layer and the second metal layer;
processing the second metal layer and the semiconductor layer to form a channel, wherein the channel divides the second metal layer into a source layer and a drain layer;
forming a protection layer on the source layer, the drain layer and an inner wall of the channel; and
forming a conductive layer on the protection layer, such that the conductive layer is connected with the source layer or the drain layer.
The present application further provides a display panel, the display panel is fabricated through the above method for processing a display pane.
Two sides of the first metal layer are coated with the light shielding layer in the present application. The light shielding layer can not only effectively shield light, prevent or reduce the generation of the leakage current; and because the light shielding layer can replace a part of the gate electrodes to provide shading, the width of the gate electrodes can be set to be smaller; meanwhile the light shielding layer has the property of insulation, the parasitic capacitances among the gate electrodes, the source electrodes and the drain electrodes may be reduced, thereby avoiding accidental writing of the pixel voltage caused by the excessive parasitic capacitance. At the same time, the drift of Vth under the impact of the bias voltage may be reduced, and the probability of image sticking is reduced.
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly described below. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art may also obtain other drawings based on these drawings without paying any creative work.
In order to make those skilled in the art better understand the solutions of the present application, the technical solutions in the embodiments of the present application are clearly described in the following with reference to the accompanying drawings in the embodiments of the present application. It is obvious that the described embodiments are only partial embodiments of the present application, and are not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without any creative work should fall within the scope of the present application.
The term “include/comprise” and its any variation in the description, claims and accompany drawings of the present application are intended to cover a non-exclusive inclusion. For example, a process, a method or a system, a product or a device including a series of steps or units is not limited to the listed steps or units, but alternatively further includes steps or units not listed, or alternatively further includes other steps or units inherent to the process, method, product or device. Moreover, the terms “first”, “second” and “third” etc. are used to distinguish different objects, and are not intended to describe a particular order.
With reference to
With reference to
S1: preparing a clean substrate 10;
alternatively, the substrate 10 is generally a glass substrate 10, and the thickness of the glass substrate 10 generally ranges from 0.52 mm to 0.58 mm.
S2: fabricating a first metal layer 20, and processing the first metal layer 20 to form a gate metal layer;
alternatively, sputtering on the substrate 10 and forming the first metal layer 20, and processing the first metal layer 20 to form the gate metal layer through processes such as exposure, development and the like.
S3: forming a light shielding layer 30 attached to the substrate 10 at a lateral side of the first metal layer 20;
it should be understood that the light shielding layer 30 is also known as the black matrix, and the material of the black matrix is a chromium-containing metal composition or a resin composition, the light shielding layer is an insulating light shielding layer. Alternatively, the light shielding layer 30 is coated on the side of the first metal layer 20.
S4: forming an insulation layer 40 on the first metal layer 20, the light shielding layer 30 and the substrate 10;
alternatively, the insulting layer 40 is disposed on the gate metal layer, so as to form a gate insulation layer. The first metal layer 20 and the light shielding layer are each disposed between the insulation layer 40 and the substrate 10; the insulation layer 40 completely covers the light shielding layer 30 and the first metal layer 20, and at least part of both two sides of the insulation layer 40 are contacted with the glass substrate 10.
S5: forming a semiconductor layer 50 on the insulation layer 40;
alternatively, the semiconductor layer 50 is formed by sputtering and coating.
S6: forming a second metal layer 60 on the semiconductor layer 50, and the semiconductor layer 50 is disposed between the insulation layer 40 and the second metal layer 60;
alternatively, the second metal layer 60 is formed through the process of sputtering.
S7: processing the second metal layer 60 and the semiconductor layer 50 to form a channel 65;
specifically, the channel 65 separates the second metal layer 60 into a source layer 62 and a drain layer 61; the processing procedures include the processes of exposure, development, and two wet Oxidation, and the process of two dry Oxidation. The probability of light entering the channel 65 is reduced through the light shielding layer 30 coated on the two sides of the first metal layer 20, thus reducing the leakage current.
The light shielding layer 30 may effectively block the passage of light, thereby reducing the projection of the backlight on the semiconductor layer, and avoiding an increase in leakage current. The light shielding layer 30 may further replace light shielding effect of partial first metal layer 20, and may appropriately reduce the width of the gate electrode, reduce the capacitance among the gate electrode, the source electrode and the drain electrode, prevent the pixel voltage from being erroneously written, and meanwhile prevent a short circuit among the source layer 62, the drain layer 61 and the gate metal layer, which improves the qualification rate of the display panel 100.
S8: forming a protection layer 70 on the source layer 62, the drain layer 61 and the inner walls of the channel 65;
alternatively, the protection layer 70 is a passivation layer, and the material of the passivation layer is silicon oxide or silicon nitride, and the protection layer 70 has an insulation protection effect.
S9: forming a conductive layer 80 on the protection layer 70, such that the conductive layer 80 is connected to the source layer 62 or the drain layer 61.
alternatively, the surface of the protection 70 is processed to form a contact hole 66, and the contact hole 66 connects the source layer 62 or the drain layer 61;
alternatively, the contact hole 66 is formed by the technologies of exposure and development.
With reference to
Two sides of the first metal layer 30 are coated with the light shielding layer 30 in the present application. The light shielding layer 30 may not only effectively shield light, prevent or reduce the generation of the leakage current; and due to the insulation property of the light shielding layer 30, the parasitic capacitance among the first metal layer 20, the source electrode and the drain electrode may be reduced, thereby avoiding accidental writing of the pixel voltage caused by the excessive parasitic capacitance. At the same time, the drift of Vth under the impact of the bias voltage may be reduced, and the probability of image sticking is reduced.
With reference to
The light shielding layer 30 includes a first light shielding layer 31 which is formed on one side of the first metal layer 20 through jet printing and a second light shielding layer 32 which is formed on the other side of the first metal layer 20 through jet printing. The thickness of the first light shielding layer 31 is smaller than the thickness of the first metal layer 20, and the thickness of the second light shielding layer 32 is smaller than the thickness of the first metal layer 20, such that the first metal layer 20 may be in contact with the insulation layer 40, thereby making the insulation layer stably cover the first metal layer 20 and the light shielding layer and be less likely to occur relative movement. The first metal layer 20 is disposed between the first light shielding layer 31 and the second light shielding layer 32.
With reference to
The material of the insulation layer 40 includes one or more type of silicon oxide and silicon nitride. Both silicon oxide and silicon nitride are characterized by high hardness, wear resistance, and oxidation resistance in high temperature.
The semiconductor layer 50 includes: an active layer 51 formed on the insulation layer 40 and an ohmic contact layer 52 formed on the active layer 51 and blocked by the channel 65. Alternatively, the active layer 51 is an I-a-Si thin film layer, and the ohmic contact layer 52 is an N+a-Si thin film layer. The ohmic contact layer 52 is divided into two portions by the channel 65, with a portion between the active layer 51 and the drain layer 61 and another portion between the source layer 62 and the active layer 51. The material of the active layer 51 is amorphous silicon or polycrystalline silicon.
Alternatively, the protection layer 70 is formed through a chemical vapor deposition film formation technology, and the material of the protection layer 70 includes one or more type of silicon oxide and silicon nitride. The chemical vapor deposition film formation technology is actually chemical vapor deposition, and this technology may be used to coat at a surface to be processed to form a film layer.
The above description is only alternative embodiments of the present application, and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements etc. made within the spirit and principles of the present application should be included in the scope of the present application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201811060540.3 | Sep 2018 | CN | national |
This application is the International Application No. PCT/CN2018/111259 for entry into US national phase with an international filing date of Oct. 22, 2018, designating US, now pending, and claims priority to Chinese Patent Application No. 201811060540.3, filed on Sep. 12, 2018, the content of which is incorporated herein by reference in its entirety.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2018/111259 | 10/22/2018 | WO | 00 |
