Claims
- 1. A method for producing a semiconductor temperature sensor, comprising the steps of:forming a plurality of PNP bipolar transistors and PMOS transistors so that a base region of each of the PNP bipolar transistors and a corresponding N-well region of each of the PMOS transistors are formed at the same time; and connecting the PNP bipolar transistors in a Darlington connection.
- 2. A method according to claim 1; wherein the step of providing a plurality of PNP bipolar transistors comprises providing a plurality of PNP bipolar transistors having a current-amplification factor greater than 20.
- 3. A method according to claim 1; wherein the step of providing a plurality of PNP bipolar transistors comprises providing a plurality of PNP bipolar transistors each having a base region having an impurity concentration less than 2×1016 cm−3.
- 4. A method for producing a semiconductor temperature sensor, comprising the steps of: forming a plurality of PNP bipolar transistors and PMOS transistors so that an emitter region of each of the PNP bipolar transistors and corresponding source and drain regions of each of the PMOS transistors are formed at the same time; and connecting the PNP bipolar transistors in a Darlington connection.
- 5. In a method for producing a semiconductor temperature sensor having a plurality of independent current sources, a plurality of PNP bipolar transistors connected to form a Darlington circuit and having main electrodes each connected to one of the current sources, each of the PNP bipolar transistors having a base electrode some of which are connected to respective main electrodes of another of the PNP bipolar transistors, a plurality of operational amplifiers having a plurality of differential input portions comprised of PMOS transistors and having a plurality of input terminals each connected to a respective one of the main electrodes of the PNP bipolar transistors which are not connected to the PNP bipolar transistor base electrodes, and a plurality of output pads each connected to a respective output terminal of each of the operational amplifiers, the improvement comprising the step of: forming the PNP bipolar transistors and the PMOS transistors so that a base region of each of the PNP bipolar transistors and a corresponding N-well region of each of the PMOS transistors are formed at the same time.
- 6. A method according to claim 5; wherein each of the PNP bipolar transistors has a current-amplification factor greater than 20.
- 7. A method according to claim 5; wherein each of the PNP bipolar transistors has a base region having an impurity concentration less than 2×1016 cm−3.
- 8. In a method for producing a semiconductor temperature sensor having a plurality of independent current sources, a plurality of PNP bipolar transistors connected to form a Darlington circuit and having main electrodes each connected to one of the current sources, each of the PNP bipolar transistors having a base electrode some of which are each connected to respective main electrodes of another of the PNP bipolar transistors, a plurality of operational amplifiers having a plurality of differential input portions comprised of PMOS transistors and having a plurality of input terminals each connected to a respective one of the main electrodes of the PNP bipolar transistors which are not connected to the PNP bipolar transistor base electrodes, and a plurality of output pads each connected to a respective output terminal of each of the operational amplifiers, the improvement comprising the step of: forming the PNP bipolar transistors and the PMOS transistors so that an emitter region of each of the PNP bipolar transistors and corresponding source and drain regions of each of the PMOS transistors are formed at the same time.
- 9. A method for producing a semiconductor temperature sensor, comprising the steps of: forming a plurality of NPN bipolar transistors and NMOS transistors so that a base region of each of the NPN bipolar transistors and a corresponding P-well region of each of the NMOS transistors are formed at the same time; and connecting the NPN bipolar transistors in a Darlington connection.
- 10. A method for producing a semiconductor temperature sensor, comprising the steps of: forming a plurality of NPN bipolar transistors and NMOS transistors so that an emitter region of each of the NPN bipolar transistors and corresponding source and drain regions of each of the NMOS transistors are formed at the same time; and connecting the NPN bipolar transistors in a Darlington connection.
- 11. A method for producing a semiconductor temperature sensor, comprising the steps of: forming a plurality of PNP bipolar transistors and PMOS transistors so that an emitter region of each of the PNP bipolar transistors and corresponding source and drain regions of each of the PMOS transistors are formed at the same time; and connecting the PNP bipolar transistors in a Darlington connection.
- 12. A method according to claim 11; wherein the step of forming a plurality of PNP bipolar transistors comprises providing a plurality of-PNP bipolar transistors having a current-amplification factor greater than 20.
- 13. A method according to claim 11; wherein the step of forming a plurality of PNP bipolar transistors comprises providing a plurality of PNP bipolar transistors each having a base region having an impurity concentration less than 2×1016 cm−3.
- 14. A method for producing a semiconductor temperature sensor, comprising the steps of: forming a plurality of NPN bipolar transistors and NMOS transistors so that an emitter region of each of the NPN bipolar transistors and corresponding source and drain regions of each of the NMOS transistors are formed at the same time; and connecting the NPN bipolar transistors in a Darlington connection.
- 15. In a method for producing a semiconductor temperature sensor having a plurality of independent current sources, a plurality of NPN bipolar transistors connected to form a Darlington circuit and having main electrodes each connected to one of the current sources, each of the NPN bipolar transistors having a base electrode some of which are connected to respective main electrodes of another of the NPN bipolar transistors, a plurality of operational amplifiers having a plurality of differential input portions comprised of NMOS transistors and having a plurality of input terminals each connected to a respective one of the main electrodes of the NPN bipolar transistors which are not connected to the NPN bipolar transistor base electrodes, and a plurality of output pads each connected to a respective output terminal of each of the operational amplifiers, the improvement comprising the step of: forming the NPN bipolar transistors and the NMOS transistors so that a base region of each of the NPN bipolar transistors and a corresponding P-well region of each of the NMOS transistors are formed at the same time.
- 16. A method according to claim 15; wherein each of the NPN bipolar transistors has a current-amplification factor greater than 20.
- 17. A method according to claim 15; wherein each of the NPN bipolar transistors has a base region having an impurity concentration less than 2×1016 cm−3.
- 18. In a method for producing a semiconductor temperature sensor having a plurality of independent current sources, a plurality of NPN bipolar transistors connected to form a Darlington circuit and having main electrodes each connected to one of the current sources, each of the NPN bipolar transistors having a base electrode some of which are each connected to respective main electrodes of another of the NPN bipolar transistors, a plurality of operational amplifiers having a plurality of differential input portions comprised of NMOS transistors and having a plurality of input terminals each connected to a respective one of the main electrodes of the NPN bipolar transistors which are not connected to the NPN bipolar transistor base electrodes, and a plurality of output pads each connected to a respective output terminal of each of the operational amplifiers, the improvement comprising the step of: forming the NPN bipolar transistors and the NMOS transistors so that an emitter region of each of the NPN bipolar transistors and corresponding source and drain regions of each of the NMOS transistors are formed at the same time.
Priority Claims (8)
Number |
Date |
Country |
Kind |
7-234463 |
Sep 1995 |
JP |
|
8-206212 |
Aug 1996 |
JP |
|
8-208619 |
Aug 1996 |
JP |
|
8-208620 |
Aug 1996 |
JP |
|
8-210258 |
Aug 1996 |
JP |
|
8-223950 |
Aug 1996 |
JP |
|
8-223952 |
Aug 1996 |
JP |
|
8-235583 |
Sep 1996 |
JP |
|
Parent Case Info
The present application is a division of prior U.S. application Ser. No. 08/712,871, filed on Sep. 12, 1996, now U.S. Pat. No. 6,046,492, which is hereby incorporated by reference, and priority thereto for common subject matter is hereby claimed.
US Referenced Citations (14)
Non-Patent Literature Citations (3)
Entry |
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D. Hodges, “Darlington's Contributions to Transistor Circuit Design”, IEEE Transactions on Circuit and Systems-I: Fundamental Theory and Applications, vol. 46, No. 1, Jan. 1999, pp. 102-104. |