Patent Application
20180076038
Disclosed embodiments relate generally to the field of manufacturing semiconductor devices. More particularly, and not by way of any limitation, the present disclosure is directed to a method for producing two n-type buried layers in an integrated circuit.
Semiconductor manufacturing requires highly controlled processing in an ultra-clean environment and can be a very expensive process. Manufacturers are constantly looking for ways to improve the flow, shorten the processing time and/or lower the costs of production for a given process, such as implanting two different buried layers on a single chip.
Disclosed embodiments provide a method of producing dual buried layers in a semiconductor chip that eliminates a number of steps from a prior process to accomplish the same result. The disclosed embodiments decrease the time necessary to produce the end product and consequently lowers the cost of production. Other advantages are discussed in the specification.
In one aspect, an embodiment of a method of forming two n-type regions in a substrate is disclosed. The method includes implanting a first n-type dopant into the substrate through openings in a dielectric layer that is patterned for a first region; forming a first photoresist layer overlying the dielectric layer, the first photoresist layer being patterned for a second region; and implanting a second n-type dopant into said substrate through openings in said first photoresist layer.
Embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like references indicate similar elements. It should be noted that different references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references may mean at least one. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
The accompanying drawings are incorporated into and form a part of the specification to illustrate one or more exemplary embodiments of the present disclosure. Various advantages and features of the disclosure will be understood from the following Detailed Description taken in connection with the appended claims and with reference to the attached drawing figures in which:
Specific embodiments of the invention will now be described in detail with reference to the accompanying figures. In the following detailed description of embodiments of the invention, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.
Turning first to
After the DNBL drive is completed, oxidation layer 404 is stripped off and a second oxidation layer 410, also 7500A thick, is grown on substrate 402. This stage of the process is shown as 400B. At the stage shown at stage 400C, oxidation layer 410 has been patterned using a photoresist layer (not specifically shown), which is then removed. A second implantation is performed through the patterned opening in oxidation layer 410 to form NBL implant 412. In at least one embodiment, the second implantation process implants antimony at a dosage of 2×1015/cm2 at an energy of 60 KV.
Once the implantation is completed, a diffusion-under-field (DUF) drive is performed to drive the two implants further into the substrate, creating the regions shown as 400D. As the DUF drive is performed, pad oxide 414 grows on the exposed silicon overlying NBL implant 412. This completes the prior process of forming the dual buried layers. While the process illustrated in
The modified process will now be explained with reference to
As seen in 100C, photoresist 106 is removed prior to implanting antimony in a blanket implant process to create NBL 108. In one embodiment, the implantation process to create NBL 108 is performed at 60 KV and implants antimony at a dosage of 2×1015/cm2. The DUF drive that previously followed the implantation of NBL 108 is not performed at this point, although it will be performed at a later time. As seen in stage 100D, a new oxidation layer is not created between the two implantation processes; rather photoresist layer 110 simply covers both oxidation layer 104 and exposed regions of substrate 102. Since photoresist 110 is a conformal layer, the topography of the photoresist 110 is not entirely smooth.
In the disclosed process, the DNBL implantation takes place through oxide layer 104 and thus requires higher energy to perform. In one embodiment, the thickness of photoresist 110 is increased to 1.5 microns. As seen in 100E, photoresist 110 has been patterned, although the underlying oxidation layer 104 has not been disturbed. The substrate is, of course, already exposed in the region where the DNBL and NBL overlap. A close examination reveals that the opening through which DNBL 112 will be formed is somewhat larger than the opening used in the prior art process; this adjustment compensates for the fact that no DNBL drive is performed in the disclosed process. One advantage of the disclosed process is that whenever a thermal process is performed on the substrate, e.g., the prior art re-growing of 7500 Å of oxide, outgassing of the dopant can occur through exposed regions and may contaminate other regions. Since in the disclosed embodiments, no thick growth of oxide is performed after the implant, little or no outgassing or cross contamination by the phosphorus occurs.
In one embodiment, the blanket implantation of phosphorus is a chain implant, with one segment implanting 1.0×1013/cm2 at 90 Kev and a second segment implanting 1.5×1013/cm2 at 1.3 MeV. The first, low energy implant will be blocked by the thick oxide layer over the DNBL region 101, but will penetrate in the overlapping region 103. The second, high energy implant will penetrate the thick oxide overlying region 101 and will penetrate deeply into the substrate in region 103. In the steps illustrated in 100F, photoresist 110 was ashed and substrate 102 was subjected to the DUF drive that was not previously performed. Note that the DUF drive will enlarge both NBL 108 and DNBL 112 by driving each further into the substrate. During this process, a thin layer of silicon dioxide 114 is also formed.
This completes the process of implanting two n-type dopants into a substrate, although this process will be understood to be part of a larger process that includes forming two n-type buried layers and forming the rest of the circuit, e.g., active devices. As seen in 100G, the oxidation layers and any other dielectric remaining on the surface of substrate 102 has been removed and an epitaxial layer 116 has been grown. As the epitaxial layer is grown, the buried implants are driven into epitaxial layer 116 to form an n-type buried layer 108 and a deep n-type buried layer 112. Depending on the specific circuit in which the disclosed dual n-type layers is being used, further processing can take many forms.
The process has been disclosed for two buried layers grown in the substrate of a silicon wafer. However, other semiconductor materials, such as germanium and selenium, can also be used in conjunction with the disclosed method. Further, this method can also be used after an epitaxial layer has been formed. Therefore, for the purposes of this application, reference to actions performed on a substrate can also be interpreted to include actions performed on an epitaxial layer. Additionally, when the disclosed implantations are performed after the epitaxial layer is formed, regions other than buried layers can be created using the disclosed process.
Applicant notes that it is possible to utilize the disclosed process, while reversing the order of the implantations, i.e., the process can implant dopants for the DNBL through openings in a photoresist layer prior to implanting dopants for the NBL through openings in the dielectric layer. However, it is important that patterns are aligned to each other so that the relationship between different regions is maintained. Since the dielectric layer is not itself patterned when implanting the DNBL region, performing the DNBL implant first would require additional actions to form alignment marks that can be used when patterning the NBL layer. By implanting NBL first, alignment marks can be formed in the dielectric layer when the pattern etch for the NBL layer is performed, such that no additional actions are needed.
Table 1 below shows a comparison of the actions performed in the prior art method and those performed in the disclosed procedures:
It can be seen in the comparison shown by this table that the changes made by the disclosed process eliminate the need for a number of actions, such as etching the oxide prior to implanting the DNBL and cleaning up after the etch is completed. There is also no need to grow a pad oxide, as a much thicker oxide already exists on top of the substrate where the DNBL is to be implanted. Additionally, the DNBL drive is removed from the process. Finally, since the first oxidation layer is not removed in the second process, there is no need to grow a second oxidation layer in preparation for the DNBL implantation. In one embodiment, the time saved in removing all of these actions amounts to approximately three days, which over the lifetime of the process can potentially save millions of dollars.
Although the process is described herein using phosphorus for the DNBL and antimony for the NBL, other n-type dopants can be used. The most commonly used n-type dopants are phosphorus, arsenic and antimony, which have atomic mass units (AMU) of 31, 75 and 121 respectively. Any of these dopants or other less commonly used n-type dopants can be used for the NBL layer, which is implanted directly into the substrate. Implanting dopants through the dielectric layer requires using high implant energy, with higher AMU species requiring higher implant energies to penetrate through the dielectric. Arsenic can be implanted in the example DNBL through the dielectric; in one embodiment using arsenic, the oxidation layer is reduced to below 5000 Å. Antimony would not generally be used to implant through the oxidation layer due to its large AMU. All of these variations fall within the scope of this disclosure.
Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or example. None of the above Detailed Description should be read as implying that any particular component, element, step, act, or function is essential such that it must be included in the scope of the claims. Reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” All structural and functional equivalents to the elements of the above-described embodiments that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Accordingly, those skilled in the art will recognize that the exemplary embodiments described herein can be practiced with various modifications and alterations within the spirit and scope of the claims appended below.
