Patent Application
20190138310
Priority is claimed to German Patent Application No. DE 102017126094.3, filed on Nov. 8, 2017, the entire disclosure of which is hereby incorporated by reference herein.
The real-time simulation of complex, dynamic models places high demands even on modern computing nodes due to the tight time constraints. In automotive hardware-in-the-loop simulations (HiL), such models are mainly used where fast control loops have to be closed. This is the case, for example, in the simulation of internal cylinder pressure sensors, which play an increasingly important role in reducing fuel consumption or exhaust emissions. But short cycle times and low latencies are also desirable for controlled systems with high dynamics, such as electric motors. These can practically no longer be implemented with CPU-based simulations.
Field Programmable Gate Arrays (FPGAs) can support computing nodes in real-time simulation by taking over computing of dynamic parts of a model. Due to the high flexibility and the possibility of parallel processing of signals, FPGAs can also be used to easily meet hard real-time requirements. The FPGAs can serve as hardware accelerators for CPUs of computing nodes. Accordingly, very dynamic parts of the environment model, for example, are stored in the FPGA so that sufficiently precise and fast response times for the ECU are guaranteed. An FPGA netlist is usually generated based on an FPGA model in a hardware description language in a build process.
The models of a controlled system are becoming increasingly complex and therefore difficult to handle due to increasing demands on accuracy. In the automotive HiL environment such models are usually created using the toolset Matlab/Simulink from The MathWorks Inc. Simulink provides a block-based view of such models in the form of a block diagram. Model parts can be combined into subsystems in a block diagram and linked to each other with signals. The data flow between these blocks is displayed via signal lines.
An FPGA-based simulation can be modelled in a block diagram with Simulink using the Xilinx System Generator (XSG) and dSPACE's FPGA Programming Blockset, analogous to CPU-based simulation.
In contrast to CPU simulation, this model is not translated into an iterative programming language, but into an FPGA netlist that describes a customer-specific digital circuit. The FPGA netlist can be translated into an FPGA configuration data stream. The FPGA configuration data stream configures an FPGA such that the circuit defined by the model at runtime is performed.
From DE102013101300A1 a method for accessing a signal value of an FPGA at runtime is known.
In an exemplary embodiment, the present invention provides a method for reading variables from a Field Programmable Gate Array (FPGA) at runtime. The method includes: calculating, in the FPGA, a first variable, wherein the first variable is associated with a first shadow register and a second shadow register, and wherein the first variable is associated with a first measurement grid and with a second measurement grid; synchronously storing, at a first point in time, all variables associated with the first measurement grid in shadow registers associated with the respective variables; synchronously storing, at a second point in time, all variables associated with the second measurement grid in shadow registers associated with the respective variables; and reading out the shadow registers independently of one another.
The present invention will be described in even greater detail below based on the exemplary figures. The invention is not limited to the exemplary embodiments. All features described and/or illustrated herein can be used alone or combined in different combinations in embodiments of the invention. The features and advantages of various embodiments of the present invention will become apparent by reading the following detailed description with reference to the attached drawings which illustrate the following:
In the following some terms are explained in the way they are to be understood herein.
Reading out a variable here is understood as reading out a value of the variable stored in a register at a certain point in time. The storage of a variable in a register is understood as the storage of the current value of the variable in a register. Variables can contain any number of bits and be distributed over several registers.
A shadow register is understood to be a register that is not necessary for the computations performed in the FPGA, but that can store values of variables independently of the current computations. The values stored in the shadow registers are not included in the current computations. Reading out of the shadow registers can be carried out using various known techniques. For example, shadow registers can be read out via a “readback mechanism” present in the FPGA. The “readback mechanism” is characterized by the fact that the outputs of the shadow registers do not have to be connected further. Consequently, no wiring effort is necessary for the implementation of the readout technology. In an alternative version, the shadow registers are connected via one or more multiplexers to an IO pin of the FPGA. This means that considerably fewer IO pins are required for readout than shadow registers. In an alternative version, the shadow registers are connected to an address decoder. The shadow registers can be read out individually via the address decoder.
A measurement grid is understood here as periodic, aperiodic or sporadic triggering of a storage and readout process.
Herein, synchronous or simultaneous means in particular that two or more actions take place in the same computing step in clocked computations. For example, the FPGA may contain a clock generator or be connected to a clock generator, wherein the clock signal from the clock generator causes the variables to be updated. Before another clock signal updates the variables again, all simultaneous or synchronous actions, e.g. synchronous storage of several variables, are performed.
A trigger signal is understood to be a signal that triggers a predetermined action. A trigger signal can, for example, cause a variable to be stored in a shadow register. Such a trigger signal can, for example, be distributed via a clock network in the FPGA. A clock network is usually used to distribute a clock signal from a clock generator and thereby control a clocked computation in the FPGA as described above. Since a large number of clock networks can be implemented in an FPGA, one or more clock networks can be used to monitor the computation and further clock networks can be used to distribute the trigger signals.
An exemplary embodiment of the present invention provides a method for reading out of a data processing device with a processor unit and an FPGA, wherein the data processing device is designed to perform the above method. Another exemplary embodiment of the present invention provides a computer program product with computer-implemented instructions which, after loading and executing in a suitable data processing device, executes the steps of the above procedure and a digital storage medium with electronically readable control signals which can interact with a programmable data processing device in such a way that the above procedure is performed.
An exemplary embodiment of the invention provides a method for reading variables from an FPGA at runtime, wherein a first variable is calculated in the FPGA, wherein the first variable is associated with a first shadow register and a second shadow register, wherein the first variable is associated with a first measurement grid, wherein at a first point in time the first measurement grid causes synchronous storage of all variables associated with the first measurement grid in a shadow register associated with the respective variables, wherein the first variable is associated with a second measurement grid, wherein at a second point in time the second measurement grid causes synchronous storage of all variables associated with the second measurement grid in a shadow register associated with the respective variable, wherein the shadow registers are read out independently of one another.
One advantage of this method is that the measurement points of the measurement grids can be located in close chronological succession to each other, since the second value can be stored before the first value has been read out. Via the independent readout the faster needed value can be read out first, regardless of the value that was stored first. It is therefore not necessary to read out the firstly stored value before the second value is stored, nor is it necessary to read out the firstly stored value before the second value.
It will be appreciated that the number of shadow registers can be increased. The number can be specified directly or indirectly by the user when creating the FPGA program. An indirect specification can, for example, be made by specifying the number of measurement grids that are to be usable at runtime.
A processor unit can be connected to the FPGA to form a data processing device and can be used to control the readout. For this purpose, the processor unit can address a readback mechanism present in the FPGA. Alternatively, a logic for outputting the stored variables that are controllable by the processor unit can be implemented in the FPGA program. Such a controllable logic can be, for example, an address decoder via which the individual shadow registers are addressable.
In an advantageous configuration, a second variable is computed in the FPGA, wherein a third shadow register is associated with the second variable, wherein the second variable is associated with the first measurement grid, wherein at the first point in time the second variable is stored synchronously with the first variable.
The advantage here is that the values of both variables are simultaneously stored. Herein, synchronous or simultaneous means in particular that both variables are stored in the same clock step during a clocked computation in the FPGA. So, the FPGA is connected to a clock generator or has an internal clock generator and in each clock step the values of the variables are updated. The first measurement grid causes two variable values which are present in the same clock step to be stored in two shadow registers.
In an advantageous configuration, the first shadow register and the second shadow register are connected in parallel.
In this case, connected in parallel means that both registers receive the same variable as data input. Storage can be caused independently for both shadow registers. For example, the first shadow register can receive a different trigger signal than the second shadow register.
In a particularly advantageous configuration, the first measurement grid stores the value of the first variable in the first shadow register and the second measurement grid stores the value of the first variable in the second shadow register.
The advantage is that each shadow register is permanently associated with a measurement grid. In a special configuration, a large number of variables receive the same number of parallel shadow registers. The number of shadow registers then determines the number of possible measurement grids. The fixed association facilitates an easy readout of the shadow registers, since each shadow register is associated with a variable and a measurement grid. For each measurement grid a separate trigger signal can be implemented to the associated shadow registers. Herein, a trigger signal is to be understood as a signal that is triggered by the measurement grid and causes the value present at the input of the shadow register to be stored. The value is then kept in the shadow register until another trigger signal arrives. Such a trigger signal can be implemented, for example, in the form of a clock network. A clock network is usually used to monitor a clocked computation in the FPGA. Since a large number of clock networks can be implemented in an FPGA, one or more clock networks can be used to monitor the computation and further clock networks can be used to distribute the trigger signals.
It will be appreciated that a larger number of shadow registers can be connected in parallel. The more parallel shadow registers are implemented, the more measurement grids with their own trigger signal can be used. In a configuration, the number of parallel shadow registers implemented for each variable is directly specified by the user when creating the FPGA program. In an alternative configuration, the number of measurement grids that is usable at runtime is specified by the user when creating the FPGA program and a shadow register is implemented for each measurement grid for each variable. For each measurement grid a clock network is implemented to distribute the trigger signal and for each variable the shadow register associated with the respective measurement grid is connected to the respective clock network.
In an alternative configuration, the first shadow register and the second shadow register are connected in series.
Herein, connected in series means that a data output of the first shadow register is connected to a data input of the second shadow register. Thus, the second shadow register can incorporate the value stored in the first shadow register. Both shadow registers are controlled with the same trigger signal.
The advantage of this configuration is that both measurement grids use the same trigger signal. Therefore, a single signal may be used for both measurement grids. This makes it possible to use more measurement grids than clock networks are available for the distribution of trigger signals. In one configuration, more shadow registers are implemented as measurement grids. For example, twice as many shadow registers as measurement grids can be implemented per variable. The number of measurement grids can be specified by the user.
In a further configuration, the first measurement grid and the second measurement grid cause the first variable to be stored in the first shadow register, wherein the value stored in the first shadow register is shifted to the second shadow register, wherein the association of the shadow registers to the measurement grids is updated accordingly.
Updating the association of the shadow registers to the measurement grids can for example take place in the form of a “stage counter”. The “Stage Counter” indicates at any time which shadow register is associated with which measurement grid. The trigger signal of the respective measurement grid is transmitted to the “Stage Counter” and the association is updated. The first shadow register is thus associated with the first measurement grid at the first point in time and to the second measurement grid at the second point in time.
With a further trigger signal, the value stored in the second shadow register is lost. Therefore, it is advantageous to implement more shadow registers connected in series. Then, for a trigger signal the value stored in a shadow register is shifted to the next shadow register, respectively. In an advantageous configuration, the number of measurement grids usable at runtime is specified by the user and twice as many shadow registers are implemented for each variable as are specified for the measurement grids.
In a further configuration, a trigger signal 10 is associated with each measurement grid.
Each measurement grid triggers the trigger signal associated with it. If the shadow registers are implemented in parallel, the trigger signal is only forwarded to the shadow registers associated with the measurement grid. If the shadow registers are implemented in series, the trigger signal is forwarded to all shadow registers and, if necessary, to a “stage counter”.
In an advantageous design, the configuration of the first variable to a measurement grid is changed at runtime.
The association of the variables to the measurement grids determines which shadow registers are read out. By changing the association at runtime, the readout effort can be adjusted dynamically, since only those shadow registers are read out whose contents are required. The change can be the association with the second measurement grid, the association with a third measurement grid, or the association with no measurement grid.
In one configuration, a readout process comprises the readout of all variables linked to a measurement grid that were stored synchronously at a certain point in time.
In an advantageous configuration, the readout sequence of the shadow registers is determined in a pre-emptive procedure.
The advantage of pre-emptive processes is that one readout process can be interrupted by another readout process. This means that data required at short notice can be read out more quickly, as there is no need to wait for the current readout process to start. The interrupted readout process can be restarted at the breakpoint and does not have to be repeated completely. Preemptive procedures are known.
In an alternative configuration, the readout sequence is determined in a non-preemptive procedure.
Non-preemptive procedures are advantageous if interrupting and/or starting readout processes means additional time and/or implementation effort. In non-preemptive procedures, readout processes are always performed entirely and are not interrupted. Non-preemptive procedures are known.
In a configuration, at least one measurement grid periodically causes a storage.
Periodic storage of the variables is advantageous if the data is to be further processed in a periodic computation. For example, the computations in the FPGA can be related to a simulation on a processor, wherein the simulation is computed in periodic time steps, wherein the variables from the FPGA are required for predetermined time steps.
In one configuration, at least one measurement grid causes aperiodic or sporadic storage.
Aperiodic or sporadic storage is advantageous if the data are only required from time to time, e.g. when predetermined conditions occur. Such conditions can be, for example, certain computation results of the FPGA computations or events such as the arrival of external signals from components connected to the FPGA or the request by a user.
In a configuration, the data stored by a measurement grid are read out in a predetermined period of time.
The readout in a predetermined period of time is advantageous if the readout values are to be further processed in a real-time context. For example, the data processing device can carry out a real-time simulation or make the read-out values available to a real-time simulation.
The signal of the first measurement grid 4 is applied to the common line 10 in a combination block 106. At a first point in time t1, the common signal 10 causes the first variable to be stored in the first shadow register 2 and the second variable 6 to be stored in the third shadow register 7. The signal of the second measurement grid 5 is also applied to the common line 10 in combination block 106. At a second point in time t2, the common signal 10 causes the value stored in the first shadow register 2 to be stored in the second shadow register 3, the first variable 1 to be stored in the first shadow register 2, the value stored in the third shadow register 7 to be stored in the fourth shadow register 8 and the second variable 6 to be stored in the third shadow register 7. The value stored at the second point in time t2 is therefore not lost but moved to the fourth shadow register 8 and the current value of the second variable is stored in the third shadow register 7.
Several FPGA programs 100 may be run simultaneously on one FPGA. For each individual FPGA program 100, a procedure in accordance with exemplary embodiments of the invention can be used independently of the others. Several FPGA programs 100 can share a clock signal of a clock block 104 or work with different clock signals. An FPGA program 100 can also be a subprogram of a larger FPGA program 100.
While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. It will be understood that changes and modifications may be made by those of ordinary skill within the scope of the following claims. In particular, the present invention covers further embodiments with any combination of features from different embodiments described above and below. Additionally, statements made herein characterizing the invention refer to an embodiment of the invention and not necessarily all embodiments.
The terms used in the claims should be construed to have the broadest reasonable interpretation consistent with the foregoing description. For example, the use of the article “a” or “the” in introducing an element should not be interpreted as being exclusive of a plurality of elements. Likewise, the recitation of “or” should be interpreted as being inclusive, such that the recitation of “A or B” is not exclusive of “A and B,” unless it is clear from the context or the foregoing description that only one of A and B is intended. Further, the recitation of “at least one of A, B and C” should be interpreted as one or more of a group of elements consisting of A, B and C, and should not be interpreted as requiring at least one of each of the listed elements A, B and C, regardless of whether A, B and C are related as categories or otherwise. Moreover, the recitation of “A, B and/or C” or “at least one of A, B or C” should be interpreted as including any singular entity from the listed elements, e.g., A, any subset from the listed elements, e.g., A and B, or the entire list of elements A, B and C.
| Number | Date | Country | Kind |
|---|---|---|---|
| 102017126094.3 | Nov 2017 | DE | national |
