Patent Application
20220058325
The present invention relates to an analog circuit recognition technique, and more particularly, to a method for recognizing various analog circuit structures.
Analog circuit designs are quite different from digital circuit designs from a layout perspective. Unlike a large-scale digital design, an analog circuit design usually has a relatively small scale, i.e., an analog circuit typically has a relatively small die size. However, its physical behavior is very sensitive to the layout geometry, e.g., parasitic coupling effect, small signal transmission, wiring crossovers, etc. Hence, area minimization is usually not a concern for an analog circuit design. A digital circuit designer can leverage mature commercial electronic design automation (EDA) tools to automate layout generation. However, the existing and popular way to generate an analog circuit layout is far from automatic. The manual, time-consuming, error-prone task highly depends on the layout designer's experience and wit. However, analog circuit design automation has become desirable.
Traditionally, analog circuitry has been manually laid out into its semiconductor mask layers for semiconductor manufacturing. This is because a human layout designer typically was experienced in analog circuit layout with prior knowledge, experience, and skill as to how the devices in an analog circuit were laid out so as to provide better performance and/or better noise immunity. The human layout designer can make some choices up front prior to laying out the analog circuitry. However, the number of choices that can be made up-front prior to layout by a human layout designer are limited. Moreover, a human layout designer requires considerable time to layout an entire analog circuit chip.
The traditional approach might not be sufficient for solving the problem effectively. Therefore, the invention proposes a new approach resulting in runtime improvement without sacrificing accuracy.
In this invention, a method for recognizing various analog circuit structures is proposed, which is executed by a computer, the method comprising using the computer to perform the following: performing a first feature extraction of a training circuit to extract all sub-circuits for generating multiple training samples; classifying the multiple training samples by a classifier to obtain classified building blocks; performing a second feature extraction of each schematic of a target circuit to convert as a feature graph and encoding the feature graph as a feature matrix; classifying the feature matrix by the classifier to generate multiple groups of classified devices based on the classified building blocks; and clustering the multiple groups of classified devices to acquire identified sub-circuits.
According to one aspect, the method further comprises storing the classified building blocks in a sub-circuit library.
According to another aspect, the classifier is used to automatically identify a type of each of all building blocks.
According to one aspect, the multiple training samples comprises a feature matrix and a label matrix, and the classifier is utilizing a classified model to classify the multiple training samples in a training sample set. The classified model includes decision tree, neural network. The classified model is performed by a machine learning algorithm. The machine learning algorithm includes a feature extraction process and the classified model.
According to one aspect, the encoded feature graph is indicated by a number, and encoded feature graph with the number is one-to-one mapping.
In the invention, a non-transitory computer-readable medium containing instructions is proposed, which when read and executed by a computer, cause the computer to execute a method for recognizing various analog circuit structures, wherein the method comprises the above-mentioned steps.
The components, characteristics and advantages of the present invention may be understood by the detailed descriptions of the preferred embodiments outlined in the specification and the drawings attached:
Some preferred embodiments of the present invention will now be described in greater detail. However, it should be recognized that the preferred embodiments of the present invention are provided for illustration rather than limiting the present invention. In addition, the present invention can be practiced in a wide range of other embodiments besides those explicitly described, and the scope of the present invention is not expressly limited except as specified in the accompanying claims.
In order to gain more experts' knowledge during analog layout generation, the present invention describes a model training and a circuit recognition process to produce a new analog circuit structure (layout). The proposed algorithm includes two major stages: the model training by an artificial intelligence (AI) model and the circuit recognition described as the following. Embodiments of the present invention may be used in a variety of layout applications.
Utilizing a design repository containing legacy design schematics/netlists, the proposed method analyzes the design data of each sub-circuit, and stores the analyzed data in a sub-circuit library (database).
As shown in
The method for recognizing various analog circuit structures in the invention comprises a step of preparing/inputting a complex analog circuit netlist and user-specified building blocks. A set of identified sub-circuits are outputted. For example, the netlist may be described in a Simulation Program with Integrated Circuit Emphasis (SPICE) format, and the design constraints are annotated into the netlist. Sub-circuits as analog circuit cells are identified as building blocks, which may refer to Wu et al., “A novel analog physical synthesis methodology integrating existent design expertise”, IEEE TCAD-2015. Each sub-circuit corresponds to some matched place-and-route (P&R) patterns which are chosen by a layout synthesizer.
In the stage of the model training 100, based on circuit information of the training circuit set, a process of a feature extraction 106 of the training circuit is performed by a feature extraction module to extract all sub-circuits for generating multiple training samples 108. Then, the training samples is classified by a model training procedure 110. For example, the model training is performed by a machine learning algorithm based on feature (characteristics) of the training samples 108. The training circuit set 104 is provided to train the neural network to classify training samples. The sub-circuit library (database) 102 provides building blocks data required for training circuit set 104. Then, the feature extraction 106 is performed by a feature extraction module to obtain training sample 108 through the training circuit inputting.
The training sample set is a set of training samples for training a classifier, such as decision tree classifier or neural network classifier, where the training sample includes a feature matrix and a label matrix corresponding to preset classification condition feature. The classifier is utilizing a classified model 112 (decision tree, neural network) to classify the training samples 108 in the training sample set according to the classification condition, and acquire a classification subset (classified building blocks). The classified building blocks are stored in the sub-circuit library (database) 102.
After the classification condition is determined, the training samples in the training sample set may be classified according to the classification condition or feature, so as to obtain a classification subset.
In the stage of the circuit recognition procedure 120, the schematic of the target circuit 122 is an input data. In the feature extraction 124, the schematic of the target circuit 122 is converted to be a corresponding connection graph or feature graph by the feature extraction module, and then the connection graph is encoded as a feature matrix. A unique matrix representation is applied to encode the connection graph or feature graph of the target circuit. Then, the device classification 126 procedure is performed by a classified model 112 to generate multiple groups of classified devices 128 based on the classified building blocks. Each building block of the groups of classified devices 128 is stored in the sub-circuit library (database) 102. Finally, the device clustering 130 procedure for the classified devices 128 is performed to acquire identified sub-circuits 132 to create an analog circuit structure.
Given a set of legacy schematics and legacy layouts, a design database is first constructed based on a connection graph representation. Since a basic connection graph can only represent logical information corresponding to a schematic, some important physical information is further annotated from the corresponding legacy layout into the connection graph. A device type is tagged on each node. The target circuit is shown in
As shown in
In the stage of the circuit recognition procedure, the schematic of the target circuit 122 is an input data. In the feature extraction 124, the schematic of the target circuit 122 is converted to be the corresponding connection graph by the feature extraction module, and the connection graph is encoded as a feature matrix. For example, as shown in
Similarly, as shown in
As shown in
The proposed method for the target circuit in which a computer performs processes of: extracting feature matrix of the target circuit; classifying the feature matrix to obtain multiple groups of classified devices; and clustering the classified devices to acquire identified sub-circuits. Therefore, a set of identified sub-circuits are outputted. The method for recognizing various analog circuit structures is finished.
As shown in
According to the invention, the machine learning algorithm includes a feature extraction process and a classification model.
The method further comprises providing a database for the machine learning algorithm. The machine learning algorithm includes at least one neural network and at least one classifier.
In the invention, a model training is performed by a machine learning algorithm to analyze and judge the feature graph of training sample, so as to automatically classify the type of the building blocks. For example, a classifier is used to automatically identify the type of the building blocks.
The algorithms of the machine learning can be executed by operation of computer. The experimental results show that the proposed method can successfully classify the training circuit, and achieve the accuracy rate of detection and classification 96% and 97% respectively, even higher accuracy.
In the present invention, the proposed algorithm may be implemented in the following experimental setup: programming language “Python 3.4”, library “Scikit-learn”, platform “2.6 GHz Intel CPU, GTX-1080 Ti GPU”, training circuits “textbooks, papers in the literature”, total training sample “385 circuits, 13580 devices”, training and testing ratio “90%:10%” and test circuits including “Folded Cascode OpAmp, Buffer Amp, Chopper OpAmp”, where Folded Cascode OpAmp uses twenty-two number of devices and twenty-seven number of sub-circuits, Buffer Amp uses forty-two number of devices and forty-one number of sub-circuits, and Chopper OpAmp uses one hundred-sixty number of devices and one hundred-sixteen number of sub-circuits.
Experimental results show in table 1. Compared with the graph-based deterministic approach, the proposed ML approach based on decision tree results in 8.5X runtime improvement without sacrificing accuracy. That is, the proposed framework achieves 8.5 speedup than the previous method.
As will be understood by persons skilled in the art, the foregoing preferred embodiment of the present invention illustrates the present invention rather than limiting the present invention. Having described the invention in connection with a preferred embodiment, modifications will be suggested to those skilled in the art. Thus, the invention is not to be limited to this embodiment, but rather the invention is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation, thereby encompassing all such modifications and similar structures. While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made without departing from the spirit and scope of the invention.
