METHOD FOR REDUCING INSERTION LOSS AND PROVIDING POWER DOWN PROTECTION FOR MOSFET SWITCHES

Abstract

An FET switch comprising a single or parallel opposite polarity FETS is illustrated with wells that are driven from internal power rails. The internal power rails are logically coupled by other driving FET switches to, in one case, the higher of a positive power supply or signal level wherein the well of the PMOS FET switch will not allow the drain/source to well diode to be forward biased. In a second case, a second power rail is logically coupled to the lower of either and input signal or ground, wherein the well of the NMOS FET will not allow the drain/source to well diode to be forward biased.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention description below refers to the accompanying drawings, of which:

FIG. 1 is schematic of a prior art p-type MOSFET switch;

FIG. 2 is a schematic/block diagram illustrating an embodiment of the present invention;

FIG. 3 is a schematic of an embodiment of the insertion loss circuit enhancement of the present invention;

FIG. 4 is a schematic of the over voltage protection/power down circuitry;

FIG. 5 is a trace illustrating the improvement in insertion loss using the present invention;

FIG. 6 is a trace illustrating the lower leakage from the input/output signals through an off switch;

FIG. 7 is a composite schematic of an embodiment illustrated in FIGS. 2, 3 and 4;

FIGS. 8A and 8B are cross section views of a PMOS and an NMOS structure that may be used for transistors M1 and M2;

FIG. 9 is a schematic showing circuitry for an NMOS and PMOS implementation of an embodiment of the invention;

FIG. 10 is a composite schematic of an insertion loss and bandwidth enhancement circuit; and

FIG. 11 is a circuit that enhances power down operations circuits for the N-type switch M2.

Claims

1. A switch comprising: a first field effect transistor, FET, having a gate, source, drain, and well, wherein an input signal is received on the drain or the source and an output signal is presented to the source or drain, respectively, when the first FET is on;a first internal power rail;a second FET arranges so that, when the first FET is turned off, a second FET is turned on coupling the well of the first FET to the first internal power rail;a third FET that couples the internal power rail to a positive power supply when the input signal goes low; anda fourth FET that couples the internal power rail to the input signal when the positive power supply goes low, wherein the well of the first FET will be maintained at the higher of the positive power supply or the A input signal.

2. The switch of claim 1 further comprising: fifth and sixth FETs of the same polarity as the first FET, the fifth and sixth arranged with their sources coupled together and the drain of the fifth coupled to the drain of the first FET and the drain of the sixth coupled to the source of the first FET; andthe wells of the fifth and the sixth FETs coupled to the first internal rail, and the sources of the fifth and the sixth coupled to the well of the first FET, wherein the fifth and sixth FETs are turned on and off with the switch being turned on and off.

3. The switch of claim 1 wherein the first FET is a P type.

4. The switch of claim 1 further comprising: a seventh FET having a gate, source, drain and well of opposite polarity from the first FET, the seventh FET having its drain and its source coupled to the drain and source, respectively, of the first FET;a second internal power rail;an eighth FET arranges so that, when the seventh FET is turned off, an eighth FET is turned on coupling the well of the seventh FET to the second internal power rail;a ninth FET that couples the second internal power rail to ground when the input signal goes low; anda tenth FET that couples the second internal power rail to the input signal if the ground signal level rises, wherein the well of the seventh FET will be maintained at the lower of ground or the A input signal.

5. The circuit of claim 4 further comprising: eleventh and twelfth FETs of the same polarity as the seventh FET, the eleventh and twelfth FETs arranged with their sources coupled together and the drain of the eleventh coupled to the drain of the seventh FET and the drain of the twelfth coupled to the source of the seventh FET; andthe wells of the eleventh and twelfth FETs coupled to the second internal rail, and the sources of the eleventh and twelfth FETs coupled to the well of the seventh FET, wherein the eleventh and twelfth FETs are turned on and off with the switch being turned on and off.

6. The circuit of claim 2 further comprising: a first enable input signal coupled to the gates of the first, fifth and sixth FETs, the enable turning on these FETs when true and off when false.

7. The circuit of claim 5 further comprising: a second enable coupled to the gates of the seventh, eleventh and twelfth FETs, the second enable turning on these FETs when true and off when false.

8. The circuit of claim 7, wherein the second enable is the logic inverse of the first enable.

9. A method for connecting an input to and disconnecting an input from an output, the method comprising the steps of: turning on first field effect transistor, FET, having a gate, source, drain, and well, wherein when the first FET is turned off;turning on a second FET coupling the well of the first FET to an internal power rail;turning on a third FET that couples the internal power rail to a positive power supply when the input signal goes low; andturning on a fourth FET that couples the internal power rail to the input signal when the positive power supply goes low, wherein the well of the first FET is maintained at the higher of the positive power supply or the A input signal.

10. The method of claim 9 further comprising the steps of: coupling the sources together of a fifth and sixth FET of the same polarity as the first FET;coupling the drain of the fifth to the drain of the first FET and the drain of the sixth to the source of the first FET; andcoupling the wells of the fifth and the sixth FETs to the internal rail, and coupling the wells of the fifth and the sixth to the well of the first FET, wherein the fifth and sixth FETs are turned on and off with the switch being turned on and off.

11. The method of claim 9 further comprising the steps of: coupling a drain and source of a seventh FET, the seventh FET having a gate, source, drain and well of opposite polarity from the first FET, to the drain and source, respectively, of the first FET;turning on an eighth FET that couples the well of the seventh FET to a second internal power rail when the seventh FET is turned off;turning on a ninth FET that couples the second internal power rail to ground when the input signal goes negative; andturning on a tenth FET that couples the second internal power rail to the input signal if the ground signal goes negative.

12. The method of claim 11 further comprising the steps of: coupling the sources together of an eleventh and twelfth FET of the same polarity as the seventh FET;coupling the drain of the eleventh to the drain of the first FET and the drain of the twelfth to the source of the seventh FET; andcoupling the wells of the eleventh and twelfth FETs to the internal rail, and coupling the wells of the eleventh and twelfth to the well of the seventh FET, wherein the eleventh and twelfth FETs are turned on and off with the switch being turned on and off.

13. The method of claim 10 further comprising the steps of: coupling a first enabled input signal to the gates of the first, fifth and sixth FETs that turns on these FETs when true and off when false.

14. The method of claim 12 further comprising: coupling a second enable to the gates of the seventh, eleventh and twelfth FETs that turns on these FETs when true and off when false.

15. The method of claim 14, wherein the second enable is the logic inverse of the first enable.