The present invention relates to a method for scaling an image frame, and more particularly to a method for scaling an image frame by using an off-screen technology.
In a typical scaling-down/scaling-up procedure for a video image frame, an on-screen resolution technology is employed to process the video image frame by a video system for a real-time display on a screen. Because the number of image frames displayed on the screen per second should be more than 30 to exempt from image delay, the compressed video images are stored in a frame buffer register in a form of a one-way queue, and then processed by the video system for display. One disadvantage thereof is the requirement for a large capacity of frame buffer register able to store considerable data at the same time. Although the image data consisting of a plurality of rows is easy to be compressed or scaled up in the horizontal dimension, it is difficult to be so processed in the vertical dimension. Therefore, the frame buffer register needs to have a memory capacity enough to store the plurality of rows of the image data. For example, when every three rows of image data are to be compressed into one row, the memory size of the frame buffer register should be capable of storing at least three rows of image data at the same time. On the other hand, for a compression rate up to five, i.e. one row from five ones of image data, the memory size of the frame buffer register is required to be capable of storing at least five rows of image data. As a result, the memory size of the frame buffer register has to be large enough for various compression rates, and thus costs a lot. The similar requirement also applies to the scaling-up situation in view of the image quality. Due to an increasing demand of high compressing rate or scaling-up rate and a memory size limitation of the frame buffer register, the scaling-down/scaling-up procedure by means of the on-screen technology will not assure high quality of a displayed image.
It is an object of the present invention to provide a method for scaling an image frame by using an off-screen technology, for which a frame buffer register of a memory size much smaller than that required by the on-screen resolution technology is enough to achieve the similar purpose, so as to be cost-effective.
In accordance with an aspect of the present invention, there is provided a method for scaling an image frame. A first-dimension and a second-dimension image scaling operations are performed on a first image portion of the stored image frame consisting of n rows and m columns of data. The first image portion includes the first to the pth rows and the first to the qth columns of data, where 1<p≦n and 1<q≦m. Then, the first-dimension and the second-dimension image scaling operations are performed on a second image portion of the image frame if p is not equal to n. The second image portion including the ath to tth rows and the first to the bth columns of data, where 1<a<t≦n, t>p, and 1<b≦m. Afterwards, the first-dimension and the second-dimension image scaling operations are further performed on a third image portion of the image frame if q is not equal to m. The third image portion includes the first to dth rows and the eth to the fth columns of data, where 1<e<f≦m, f>q, and 1<d≦n.
Preferably, the scaling operations are performed longitudinally. For instance, if t is not equal to n, an image portion of the image frame including at least the nth row and the first to the gth columns of data, where 1<g≦m, should be performed thereon the first-dimension and the second-dimension image scaling operations after the second image portion but prior to the third image portion will be the one.
Preferably, g=b=q, a=p+1, and e=q+1. More preferably, t=2p and f=2q.
Finally, the first-dimension and the second-dimension image scaling operations are performed on an image portion of the image frame including at least the nth row and the mth column of data.
In accordance with the present invention, the first-dimension and the second-dimension image scaling operations are preferably performed for all of the n rows and m columns of the image frame longitudinally. The first row can be the topmost row or the bottommost row, and the first column can be the leftmost column or the right most column the image frame. In addition, the image portions are preferably stored in a one-way queue to proceed the first-dimension and the second-dimension image scaling operations.
Preferably, each selected image portion consists of at least two rows and at least two columns of data to proceed a horizontal dimension and a vertical dimension scaling operations.
In an embodiment, each of the first-dimension and the second-dimension image scaling operations is performed by weighted average, interpolation, extrapolation or a combination thereof.
In accordance with another aspect of the present invention, there is provided a method for scaling an image frame. The image frame is divided into a series of first image portions horizontally adjacent to one another, and each of the first image portions is divided into a series of second image portions vertically adjacent to one another. A first-dimension and a second-dimension image scaling operations are performed on each of the second image portions one by one of the second image portions of the same first image portion and one by one of the first image portions, until all of the second image portions of the first image portions of the image frame complete the first-dimension and second-dimension image scaling operations.
In accordance with another aspect of the present invention, there is provided a method for scaling an image frame. An image frame consisting of n rows and m columns of data is stored into a storage device. The image frame is divided into a plurality of image portions. The first one of the image portions includes at least the first row and the first column of the image frame, a second one of the image portions includes at least the nth row and the first column of the image frame, a third one of the image portions includes the first row and the mth column of the image frame, and a fourth one of the image portions includes the nth row and the mth column of the image frame. Then, the first, second, third and fourth ones of the image portions are picked in sequence from a frame buffer register to be performed thereon an image scaling operation, and then cleared from the frame buffer register.
In an embodiment, the image frame includes a fifth image portion vertically between the first and second ones of the image portions, which is picked following the first one of the image portions and prior to the second one of the image portions. Furthermore, the image frame includes a sixth image portion horizontally between the first and third ones of the image portions, which is picked following the second one of the image portions and prior to the third one of the image portions.
The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:
a) is a schematic hardware structure for implementing the image-frame scaling method according to the present invention;
b) schematically illustrates a basic concept of the off-screen technology according to the present invention
a) to 2(j) illustrate a preferred embodiment of the image-frame scaling method according to the present invention;
a) to 4(c) are flowcharts illustrating a further preferred embodiment of the image-frame scaling method according to the present invention; and
a) to 5(n) are schematic diagrams illustrating the transmission sequences of image portions of an image frame to a frame buffer according to the method of
Referring to
b) schematically illustrates a basic concept of the off-screen technology according to the present invention. The image frame S is divided into a plurality of image portions S1 traverse adjacent to one another. The image portions S1 are one by one processed by the system 10 to perform a scaling up or a compressing operation, and the respective scaled image portions D1 are combined to form the scaled image frame D. The data format of the image frame S or the processed image frame D can be selected from YUV422, RGB15, RGB16, RGB32, YCbCr420, and the like.
It is known to a person skilled in the art that the memory size required for the frame buffer register 3 can be considerably reduced due to the relatively small image portion S1 by using such off-screen technology. In addition, the memory size required for the frame buffer register 3 does not have to vary with the compression ratio. Therefore, the frame buffer register required by the present method is more cost-efficient than the prior art. More specifically, the image scaling implementation in a vertical dimension is easier than in the prior art.
Please refer to
In accordance with the embodiment, each of the image portions B11, B12, B13, B21, B22, B23, B31, B32, B33 and B34 preferably consists of at least two rows and at least two columns of data. The numbers of rows and/or columns of each image portion are dependent on user's requirement and size of the frame buffer register 3. In order to make the scaled image look more smooth and natural, one or more interfacing rows between two adjacent image portions can be included in both of the image portions to be processed twice. It is also preferred that each of the image portions is of the same size. The horizontal and vertical image scaling operations are known to those skilled in the art. For example, it can be a weighted average, interpolation or extrapolation algorithm, or a combination thereof.
The above embodiment is illustrated by referring to a procedure for processing image portions in a sequence from B11 to B34. It is understood that the processing sequence can also be from B34 to B11 by way of B33, B32, B31, B23, B22, B21, B13 and B12. Alternatively, the sequence can be from B31 to B13 or from B13 to B31.
A second preferred embodiment of the present invention will be illustrated with reference to
A third preferred embodiment of the present invention will be depicted with reference to
The steps for performing this embodiment are shown in the flowcharts and described hereinafter assuming i>1 and j>1.
In Step (b1), the image frame is stored into a memory by a microprocessor. A small block of the image frame consisting of the first row and the first column of data is picked into the frame buffer register in Step (b2). Then, Steps (b5) and (b6) are executed according to the judging criteria of Step (b4). Step (b5) is repetitively executed for image blocks of the same row but adjacent columns until the image block consisting of the first row and the jth column has been stored to the frame buffer register. Step (b6) is executed to store image blocks consisting of the second row and the first to jth columns. Step (b6) will be repetitively executed until the image block consisting of the ith row and the jth column is stored to the frame buffer register on the basis of the judging criteria of Step (b8), thereby storing the complete image portion consisting of the first to the ith rows and the first to the jth columns of data to the frame buffer register. Meanwhile, Steps (b9) and (b10) are executed to complete the scaling operation of the image portion.
The above steps are repeated for the following image blocks. If the selected image portion consists of less than i rows and/or j columns, Step (b3), Step (b7) and/or Step (b11) are used to determine whether the selected image portion is the last one of the image frame, i.e. whether the selected image portion includes the rth row and the cth column of data. If negative, the previous steps are properly repeated. If positive, the entire scaling operation of the image frame is completed after the last image frame is scaled in the Step (b15).
a) to 5(n) are schematic diagrams illustrating the transmission sequences of image portions of an image frame to a frame buffer block by block according to the method of
As shown in
From the above description, it is understood that a relatively small memory size of a frame buffer register is used to achieve a high compressing rate or scaling-up rate according to the present invention without deteriorating the quality of a displayed image.
While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
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91104891 A | Mar 2002 | TW | national |
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Number | Date | Country | |
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20030174148 A1 | Sep 2003 | US |