This application is related to Japanese Patent Application No. 2004-065624 filed on Mar. 9, 2004, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
The present invention relates to a method for simulating degradation of circuit characteristics caused by hot-carrier degradation in a MOS transistor in a circuit constituted by the MOS transistor. The present invention particularly relates to enhancement of accuracy in the simulation.
As the density and integration level of semiconductor integrated circuit devices have increased and the devices have been miniaturized, the sizes of metal oxide semiconductor (MOS) transistors constituting the devices have been greatly reduced. With this reduction in the sizes of the MOS transistors, especially reduction in the channel length, hot-carrier degradation, which is a large issue in the reliability of the MOS transistors, has become more serious.
This hot-carrier degradation occurs when electrons and holes (which will be correctively referred to as “hot carriers”) with high energy are generated by a high electric field in a drain end of a MOS transistor and these hot carriers causes degradation of properties of a gate oxide film. This hot-carrier degradation has a plurality of degradation modes. Out of these degradation modes, in a degradation mode in which substrate current is at the maximum, drain current decreases with time in both an n-MOS transistor and a p-MOS transistor. This results in an occurrence of degradation, i.e., the delay time of a circuit increases with time. When the increase of the delay time exceeds a certain amount, a timing error occurs during signal input/output operation within a semiconductor integrated circuit or between the circuit and the outside. This causes a malfunction of a whole system in which the semiconductor integrated circuit is incorporated.
On this hot-carrier degradation, a conventional hot-carrier reliability evaluation using an accelerated stress test under a DC condition of a MOS transistor has been performed. In this conventional evaluation, the fabrication process is optimized to meet requirements of the hot-carrier evaluation so that the reliability of products is enhanced.
In recent years, however, the conventional hot-carrier reliability evaluation performed under a DC condition has a difficulty in satisfying the requirements of the evaluation. In view of this, new techniques with which a simulation of hot-carrier degradation in a semiconductor integrated device (hereinafter, referred to as a “circuit reliability simulation”) is performed so as to enhance the reliability of products have been devised. In a circuit reliability simulation, circuit operation after hot-carrier degradation is simulated using a hot-carrier lifetime model and parameters of a circuit simulator SPICE after the degradation based on voltages at terminals and current values in a transistor calculated by the SPICE.
Typical circuit reliability simulators are a BERT (see reference 1, R. H. Tu et al., Berkeley reliability tools—BERT, IEEE Trans. Compt.—Aided Des. Integrated Circuits & Syst., the United States, October 1993, Vol. 12, No. 10, pp. 1524-1534) developed by the University of California at Berkeley or its commercially-available counterpart, BTABERT. These circuit reliability simulation techniques are used to predict a degradation/failure part of a semiconductor integrated circuit so that measures are taken for this predicted part during the design of the circuit. This enables establishment or design of the reliability.
Examples of the method for simulating hot-carrier degradation in a MOS transistor include a method described in reference 2 (Kuo et al., IEEE Trans. Electron Devices, the United States, July 1988, Vol. 35, pp. 1004-1011). A hot-carrier lifetime model used by a circuit reliability simulator for implementing this method has the following features:
Hot-carrier degradation in a MOS transistor is evaluated by using the ratio ΔId/Id of the amount ΔId of a change in drain current to initial drain current Id and other values. Under static hot-carrier stress conditions using direct current (DC), the hot-carrier degradation rate ΔId/Id is expressed by the following equation (1):
ΔId/Id=A·tn (1)
Suppose the stressing time until the rate of the change in drain current (i.e., hot-carrier degradation rate) reaches a given value (ΔId/Id)f is transistor lifetime τ, the following equation (2) is derived from equation (1)
(ΔId/Id)f=A·τn (2)
Time t until (ΔId/Id)f=10%, for example, is defined as lifetime τ by using equation (2).
According to reference 2, lifetime τ of a MOS transistor is given by the following Equation (3) regarding an experiment using a hot-carrier lifetime model
τ=((ΔId/Id)f)l/n·H·W·Isub−m·Idm−1 (3)
I-V characteristics of a MOS transistor after degradation can be simulated using a ΔId model. Examples of a simulation method using the ΔId model include a method disclosed in reference 3 (Quader et al., IEEE Trans. Electron Devices, the United States, December 1993, Vol. 40, pp. 2245-2254.)
In a ΔId model, degradation amount ΔId of drain current is added to fresh drain current (i.e., initial drain current) before stressing, thereby simulating drain current Id′ after degradation, as expressed by the following equation (4):
Id′=Id(Vds, Vgs)+ΔId(Age, Vds, Vgs) (4)
To calculate Age in a circuit under dynamic stress conditions with alternating current (AC), the following Equation (5), which is an integration regarding time, is used.
Age=∫[(W·H)−1·Isubm·Idl−m]dt (5)
During the simulation, a SPICE model is used to calculate drain current Id in Equation (3) or (5). As an example of this SPICE model, a Berkeley Short-Channel IGFET Model (BSIM) technique described in, for example, reference 4 (Sheu et al. IEEE J. Solid-State Circuits, the United States, August 1987, Vol. SC-22, pp. 558-566) is used.
During the simulation, a substrate current model is used to determine substrate current Isub in Equation (3) or (5). As an example of the method for calculating substrate current Isub, a method disclosed in, for example, reference 5 (Chan et al. IEEE Electron Device Lett., the United States, December 1984, Vol. EDL-5, pp. 505-507) is used.
This substrate current model is expressed by the following equation (6):
Isub=(Ai/Bi)·(Vds−Vdsat)·Id·exp(−Bi·lc/(Vds−Vdsat)) (6)
The condition necessary for drain junction depth Xj to appear in Equation (7) is that the vertical electric field in the drain end can be disregarded at drain junction depth Xj. An example of a method for deriving Equation (7) is disclosed in reference 6 (Y. Taur et al., Fundamentals of Modern VLSI Devices, the United States, Cambridge University Press, 1998, pp. 154-158.) Characteristic length lc given by Equation (7) is not dependent on the voltages at respective terminals of a MOS transistor. However, in practice, lc is dependent on the voltages at terminals. Therefore, in the circuit reliability simulator BTABERT described above, a model equation for lc having dependence on drain voltage Vds is used as expressed by the following equation (8):
lc=(lc0+lc1·Vds)·(Tox)1/2 (8)
Hereinafter, a method for extracting parameters lc0 and lc1 and constant Ai mentioned above from experimental data will be described specifically.
When the coordinate axes are set in the manner described above, according to Equation (6), the intercepts (y-axis intercepts) of the lines fitted to the data regarding the measurement points are In (Ai/Bi) (where ln is a natural logarithm) and the slopes of the respective lines are −Bi·lc as long as lc and Ai are constant. Accordingly, lc and Ai are obtained from values of ln (Ai/Bi) and −Bi·lc. For data regarding measurement points at drain voltages Vds, parameters lc0 and lc1 and constant Ai in equations (6) and (8) are determined with a method of least squares. Reference numeral 22 in
First, at step S1, fresh drain current is simulated using transistor parameters before stressing which have been extracted beforehand.
Next, at step S2, substrate current Isub is simulated based on Equations (6) and (8) of the substrate current model, parameters lc0 and lc1 determined by the method described with reference to
Then, at step S3, Age, which indicates degradation of a transistor based on Equation (5), is calculated by performing time integration on a function of drain current Id and substrate current Isub in a circuit. In this calculation, drain current Id simulated at step S1 and substrate current Isub simulated at step S2 are used.
Thereafter, at step S4, hot-carrier degradation (specifically drain current Id′ after degradation) in a transistor is simulated using Equation (4) based on Age calculated at step S3.
However, with the conventional method for simulating hot-carrier degradation, the calculation results on substrate current Isub obtained using the conventional substrate current model deviate from the actually-measured values, as shown in
It is therefore an object of the present invention to implement a highly-accurate simulation of hot-carrier degradation widely applicable by creating and using a new high-precision substrate current model.
In order to achieve this object, the present inventor conducted a study to find causes of the lack of precision of a conventional substrate current model, and finally obtained the following findings:
(A) Equation (8) showing dependence of characteristic length lc on a terminal voltage in Equation (6) of a substrate current model used in a conventional method for simulating hot-carrier degradation is merely an approximation of a primary expression regarding only drain voltage Vds and therefore lacks a physical basis.
(B) The assumption that Ai is a constant in Equation (6) has no physical basis.
In view of the findings, the present inventor devised and applied a new substrate current model having a physical basis, to solve the problem of the lack of accuracy in simulating hot-carrier degradation.
Specifically, a method for simulating the reliability of a semiconductor device according to the present invention is a method used to simulate the reliability of a semiconductor device based on a predicted value of a substrate current Isub of a MOS transistor constituting the semiconductor device, wherein in calculating the substrate current Isub using a substrate current model equation expressed as
Isub=(Ai/Bi)·(Vds−Vdsat)·Id·exp(−Bi·lc/(Vds−Vdsat))
In the method of the present invention, the function lc [lc0+lc1·Vgd] is preferably proportional to (lc0+lc1·Vgd)1/4.
In the method of the present invention, the model parameter Ai is preferably a function Ai=Ai [lc0+lc1·Vgd] of the primary expression (lc0+lc1·Vgd) regarding the gate-drain voltage Vgd. In this case, the function Ai [lc0+lc1·Vgd] is preferably proportional to (lc0+lc1·Vgd)Ai1 (where Ai1 is a model parameter).
According to the present invention, model equations showing dependence on terminal voltages with physical bases are used for lc and Ai in Equation (6) of the substrate current model, so that calculation results on the substrate current less deviate from the actually-measured values. Consequently, hot-carrier degradation in a MOS transistor is simulated with high accuracy. In addition, this simulation of hot-carrier degradation is applicable in a wide range.
As described above, the method for simulating the reliability of a semiconductor device according to the present invention is useful because errors in a hot-carrier simulation for a MOS transistor are reduced when the inventive method is applied to, for example, a method for simulating hot-carrier degradation in a semiconductor integrated circuit.
Prior to description of a method for simulating the reliability of a semiconductor device according to an embodiment of the present invention, a physical basis of a substrate current model according to the present invention will be described with reference to the drawings and then equations of the substrate current model of the present invention will be described.
As shown in
Carriers in a channel 5 of the MOS transistor operating in the saturation region are predominantly affected by a longitudinal (vertical) electric field until the carriers reach a point 6 where the velocity of the carriers is saturated. On the other hand, the intensity of a lateral (horizontal) electric field in the channel 5 is low, carriers in the channel 5 flow in the surface of the silicon substrate 1, affected by the longitudinal electric field in the gate oxide film 3. However, as the carriers approach the drain region 4, the lateral electric field intensity increases so that the mobility velocity is saturated. In a velocity saturation region extending from the point 6 at which the velocity of carriers is saturated to the drain region 4, carriers flow toward the drain region 4 at a constant saturation velocity Vsat. In this velocity saturation region, the downward longitudinal electric field decreases with increasing proximity to the drain region 4 whereas the lateral electric field increases. Therefore, the electric field intensity in the velocity saturation region exhibits a two-dimensional distribution. As a result, a carrier flow path 7 from the point 6 at which the velocity of carriers is saturated to the drain region 4 extends as deep as drain junction depth Xj from the surface of the silicon substrate 1. In part of the velocity saturation region closer to the drain region 4, the direction of the longitudinal electric field is reversed, thus forming a carrier-depletion region 8.
Drain junction depth Xj appears in Equation (7) of the conventional model regarding characteristic length lc used in Equation (6) of the substrate current model because it is assumed that the depth at which the longitudinal electric field in the drain end can be disregarded is equal to drain junction depth Xj. However, from the consideration based on the carrier distribution in the velocity saturation region, the depth at which the longitudinal electric field in the drain end can be disregarded is not drain junction depth Xj but the depth Xd of the carrier-depletion region 8. This is because the lateral electric field is dominant in the carrier flow path 7 and thus the longitudinal electric field therein can be disregarded. In view of this, in the inventive substrate current model, characteristic length lc is modeled as the following equation (9):
lc=(εSi·Tox·Xd/εox)1/2 (9)
In the inventive substrate current model, the dependence of lc and Ai in Equation (6) on gate voltage Vgs and drain voltage Vds is modeled as described below. Suppose the carrier density in the carrier flow path 7 is constant in the drain end and this carrier density is nc(/cm3). In addition, suppose the carrier density is approximately zero in the carrier-depletion region 8 and an upward longitudinal electric field corresponding to the charge density equal to the decreased amount of the carrier density, −nc, occurs. This upward longitudinal electric field is generated by positive charge in the drain region 4. Based on these suppositions, the longitudinal electric field in the drain end is expressed by the following equation (10):
Ex(0)=−q·nc·Xd/εSi (10)
ø(0)=ø(Xd)−(p0+p1·Vgd) (12)
If Xd, ø(0) and ø(Xd) are removed from Equations (9), (11) and (12), the following equation (13) is established
lc=[2εSi3/(εox2·q·nc)]1/4·(p0+p1·Vgd)1/4·(Tox)1/2=(lc0+lc1·Vgd)1/4·(Tox)1/2 (13)
Parameters lc0 and lc1 are expressed using the same symbols as parameters lc0 and lc1 in Equation (8) of the conventional substrate current model but are different from lc0 and lc1 in Equation (8).
As described above, in the inventive substrate current model, lc in Equation (6) is modeled using Equation (13) including parameters lc0 and lc1 given by Equations (14-1) and (14-2), respectively.
On the other hand, in the inventive substrate current model, Ai in Equation (6) is modeled in the following manner. According to a research done by the present inventor, Ai is not such a constant as that used in a conventional technique but a function of the carrier density in the surface of a silicon substrate. The carrier density in the silicon substrate surface is a function of surface potential ø(0), so that Ai is assumed to be a function of gate-drain voltage Vgd and is expressed by, for example, the following equation (15):
Ai=Ai0·(lc0+lc1·Vgd)Ai1 (15)
In the method for simulating hot-carrier degradation in a MOS transistor using the substrate current model according to the present invention, Equations (13) and (15) of the inventive model regarding lc and Ai in Equation (6) of the substrate current model are used to simulate hot-carrier degradation.
Hereinafter, a method for simulating hot-carrier degradation in a MOS transistor using the inventive substrate current model, i.e., a method for simulating the reliability of a semiconductor device according to an embodiment of the present invention, will be described.
First, a method for extracting parameters (model parameters) lc0, lc1, Ai0 and Ai1 in the inventive substrate current model from experimental data will be described specifically.
When the coordinate axes are set in the manner described above, i.e., natural logarithms are plotted on the ordinate, according to Equation (6), the intercepts (y-axis intercepts) of the lines fitted to the data regarding the measurement points are ln (Ai/Bi) (where ln is a natural logarithm) and the slopes of the respective lines are −Bi·lc. Accordingly, lc and Ai at gate-drain voltages Vgd are obtained from ln(Ai/Bi) and −Bi·lc. For the data regarding the measurement points at gate-drain voltages Vgd, parameters lc0 and lc1 in Equation (13) and parameters Ai0 and Ai1 in Equation (15) are determined with a method of least squares.
In
In
As shown in
To determine parameters lc0, lc1, Ai0 and Ai1 in Equations (13) and (15), a method of performing numerical calculation equivalent to the plotting, a method of optimizing parameters by numerical repetitive calculation using a method of nonlinear least squares, or a method in which these methods are combined, for example, can be used, instead of the method of using a plot as described above. If part or the all of the methods for determining parameters lc0, lc1, Ai0 and Ai1 are incorporated in parameter-extracting software as programs, part of or the entire calculation of parameters lc0, lc1, Ai0 and Ai1 can be automated.
First, at step S11, fresh drain current Id is simulated using transistor parameters before stressing which have been extracted beforehand.
Next, at step S12, substrate current Isub is simulated based on Equations (6), (13) and (15) of a substrate current model and parameters lc0, lc1, Ai0 and Ai1 determined by the method described with reference to
Then, at step S13, Age, which indicates degradation of a transistor based on Equation (5), is calculated by performing time integration on the function of drain current Id and substrate current Isub in a circuit. In this calculation, drain current Id simulated at step S11 and substrate current Isub simulated at step S12 are used.
Thereafter, at step S14, hot-carrier degradation (specifically drain current Id′ after degradation) in a transistor is simulated using Equation (4) based on Age calculated at step S13.
As already described above, Equations (13) and (15) of the substrate current model (equations regarding terminal voltage dependence) of the present invention for determining lc and Ai in Equation (6) of the substrate current model shows a function of gate-drain voltage Vgd and has a physical bases, unlike the conventional equation (8) showing dependence of lc on the drain voltage, for example. Accordingly, as shown in
Specifically, an accurate simulation of hot-carrier degradation is needed when drain voltage Vds is lower than that during stressing, i.e., at about a level in actual use. On the other band, in the substrate current model of the present invention, the accuracy is high when drain voltage Vds is low. Consequently, Age is calculated with high accuracy at step S13 in the flowchart shown in
In this embodiment, as shown in Equation (13), characteristic length lc is expressed using a function which is proportional to (lc0+lc1·Vgd)1/4. Alternatively, another function lc[lc0+lc1·Vgd] of primary expression (lc0+lc1·Vgd) regarding Vgd may be used instead.
In this embodiment, as shown in Equation (15), parameter Ai is expressed using a function proportional to (lc0+lc1·Vgd)Ai1. Alternatively, another function Ai[lc0+lc1·Vgd] of primary expression (lc0+lc1·Vgd) regarding Vgd may be used instead.
Number | Date | Country | Kind |
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2004-065624 | Mar 2004 | JP | national |