Claims
- 1. A method of testing a field programmable gate array including a plurality of programmable logic blocks, comprising the steps of:
- configuring said programmable logic blocks as an iterative logic array including establishing a first group of said blocks as test pattern generators, output response analyzers and helper cells for completing a built-in self test without adding area overhead to the field programmable gate array or any circuit implemented therein;
- initiating said built-in self-test;
- generating test patterns with said test pattern generators; and
- analyzing a resulting response with said output response analyzers in order to produce a pass/fail indication.
- 2. The method set forth in claim 1, wherein said configuring further includes establishing a second group of said programmable logic blocks as blocks under test.
- 3. The method set forth in claim 2, including repeatedly reconfiguring each block under test in order to test each block under test completely in all possible modes of operation.
- 4. The method set forth in claim 3, including repeatedly rearranging programming of said first and second groups of said programmable logic blocks so that all of said programmable logic blocks are established as blocks under test at least once.
- 5. The method set forth in claim 4, including repeatedly reconfiguring each block under test in order to test each block under test completely in all possible modes of operation following each rearrangement of said first and second groups of said programmable logic blocks.
- 6. The method set forth in claim 1, further including reading results of said built-in self-test.
- 7. The method set forth in claim 5, further including reading results of said built-in self-test.
- 8. The method set forth in claim 1, wherein said test patterns being generated are exhaustive.
- 9. A field programmable gate array including a plurality of programmable logic blocks configured to comprise:
- a test pattern generator;
- an output response analyzer;
- a helper cell;
- a plurality of blocks under test;
- a memory for storing test patterns and configurations to provide exhaustive testing of each block under test; and
- an iterative logic array for completing a built-in self-test.
Parent Case Info
This is a continuation-in-part application for U.S. patent application Ser. No. 08/595,729, filed Feb. 2, 1996 entitled "Method for Testing Field Programmable Gate Arrays".
US Referenced Citations (19)
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
595729 |
Feb 1996 |
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