METHOD FOR THE CLOSED-LOOP CONTROL OF A BUCK CONVERTER AND ARRANGEMENT FOR IMPLEMENTING THE METHOD

Abstract

A method for regulating a buck converter, in which the amount of the output volume is adjusted via a controlled switching, comprising a pulse sequence showing a pulse rate and being pulse width modulated, of a conductivity, which is switched serially and drops over an output voltage, and an arrangement with a control input and with a control output, between which an analog-to-digital converter, a non-linear amplifier, an IIR filter, and a pulse width modulation circuit is switched, allow a quick reaction upon a load transient by which the regulation of the output voltage at a buck converter occurs faster and with less overshooting. This is attained such that the sample rate is adjusted greater than the pulse rate and the pulse values of the pulse sequence are controlled during the cycle duration.

Description

The invention relates to a method for regulating a buck converter, in which the amount of the output voltage is adjusted at an input voltage via a controlled switching of an inductivity, switched serially with a load and over which the output voltage drops, using a pulse sequence showing a pulse rate and pulse width being modulated. Here, the output voltage is scanned with a sample rate, its value is digitized, and thus the pulse width is adjusted.

The invention also relates to an arrangement for regulating a buck converter, comprising a control input for a pulse width modulated pulse sequence with a pulse rate and a voltage output. The arrangement comprises a control input, which can be connected to the voltage output of the buck converter, and is provided with a control output, which can be connected to the control input of the buck converter. A non-linear amplifier, an IIR filter, and a pulse width modulation circuit are switched between the control input and the control output. Furthermore, a pulse rate clock generator is provided, determining the pulse rate.

Using a known buck converter, a controlled output voltage can be generated from an input voltage. Here, the amount of the output voltage is always lower than the amount of the input voltage. The amount of the output voltage is adjusted by a controlled switching on and off using at least one switch.

In an embodiment of prior art, two switching transistors are provided, each respectively switching alternating. Both transistors are connected with their source-drain paths in a current circuit between the input voltage and the ground. An inductivity is connected therebetween, which is switched serially with a load resistor, over which the output voltage drops. A capacity is switched parallel in reference to the load resistor.

During the period the first transistor is switched on, namely the one located at the side of the input voltage, a load current flows through the inductivity and through the load resistor. The second transistor is blocked. During the period the first transistor is switched off, the second transistor is switched on. Now the energy stored in the inductivity is drained. The current flows through the consumer, however now through the second transistor and out of the capacity.

By modifying the switch on and switch off periods of the transistors the output voltage can be adjusted and controlled by adjusting these periods using settings in turn influenced by the output voltage itself. Here, the regulation occurs in a known fashion by pulse width modulation (PWM) of the control pulses at the gates of the transistors.

An arrangement for controlling a buck converter is known for example from ADP 1872 of Analog Device Inc.

In a digital solution of such a regulation (Digital Control Loop) the output voltage is subjected to an analog-to-digital conversion. Here, the digital voltage value is scanned with a sample rate and supplied via a non-linear amplification and filtering via an infinite impulse response filter (UR filter) to a pulse width modulation control in order to adjust the pulse width of the gate pulse at the two transistors. Here, the sample rate of the analog-to-digital conversion, not least due to the common use of the same clock base, is identical to the pulse rate of the gate pulses. In other words, the duty cycle of the series of gate pulses, with their duration being modulated, which represents the pulse width modulation, is equivalent to the sample cycle between two samples of the analog-to-digital converter. This leads to the pulse widths during the duty cycle being adjustable only at its beginning.

In a rapid change of load (load transient), with considerable changes of the output voltage occurring within the duty cycle, the pulse width modulation cannot react to such load transients, namely only via the next sample in the next duty cycle. This leads to a high sluggishness and the control overshooting.

The invention is now based on the objective to provide a method and an arrangement by which rapid reaction can occur for any load transient and this way the control of the output voltage at a buck converter occurs quicker and with less overshooting.

This objective is attained in a method such that the sample rate is adjusted greater than the pulse rate and the pulse width of the pulse sequence is controlled during the duration of the period. With higher sample rates it is possible, in case of large load transients, to determine the hereby triggered rapid change of the output voltage even during the period of the pulse sequence, i.e., between the pulses, and to adjust the pulse width also between the pulses to the actual (in large transients very rapid changes of voltage). This way, the control is switched very quickly and overshooting is reduced or prevented to a large extent.

Preferably the sample rate amounts from 2 to 100 times the pulse rate. It has proven very well functional when the sample rate amounts to 32 times the pulse rate.

Due to the fact that the scanning with a sample rate relatively high in reference to the pulse rate (over-sampling) yields a plurality of values, this leads to inhomogeneous control processes. This way the output voltage “ripples” even in a steady state, due to the constant switching of the transistors. Due to the high scanning rate even such normal voltage changes are registered as deviating from the norm and the control is activated. In order to avoid such erratic control behavior it is beneficially provided that the digital signal generated by the sample rate is subjected to a digital reduction via filtering such that sample values are filtered out which are to be allocated to an integer multiple of the sample frequency according to the sample rate. This beneficially occurs via moving average filters known per se. This comprises several filter maxima at the integer multiples of the sample frequency.

In one embodiment of the method it is provided that a reduction rate is programmed in the moving average filter, by which the digital values are filtered out using the adjusted reduction rate.

This way it is also possible that the reduction with the first reduction rate can be performed during the periods with essentially constant load, i.e., with a first transient, and with a second reduction rate during the periods of load changes, i.e., with a second transient higher in reference to the first transient, with the second reduction rate being smaller than the first reduction rate. In case of rapid changes of the output voltage the many intermediately determined digital values are valuable as the control parameter, because they can be used to determine the very rapidly occurring changes. For this reasons, using this variant of the method the reduction of the values can be reduced so that here a greater number of values is available for the control parameter.

With regard to the arrangement, the objective is attained such that a moving average filter is switched between the analog-to-digital converter and the non-linear amplifier. Furthermore, a sample rate clock generator is provided, which adjusts a sample rate higher in reference to the pulse rate. Using its sample rate, the analog-to-digital converter, the moving average filter, the non-linear amplifier, and the IIR filter are controlled. The pulse rate clock generator is connected to the pulse width modulation circuit and the pulse width modulation circuit is embodied continuously, i.e., it can be controlled with regard to the pulse width even during the pulse duty cycle. The analog-to-digital converter is therefore operated with the higher sample rate (over-sampling) and thus it is capable, even within the duty cycles of periods of the pulse sequence by which the transistors are controlled, to provide values of the deviation from the rule, i.e., the output voltage or the difference of the output voltage from a target value. This way it is possible to adjust the pulse width even during the period to the changes of the output voltage, which particularly in case of high transients leads to a quick adjustment.

In a beneficial embodiment of the arrangement it is provided that the moving average filter comprises two moving average filters or also two filter paths with differently programmable reduction rates. The filter can therefore be switched between two reduction rates, depending on the speed of the change of deviations from the rule. This way it is possible, in case of high transients, to provide a larger number of scanning values for the deviation from the rule.

The invention shall now be explained in greater detail using an exemplary embodiment. In the accompanying drawings it shows

FIG. 1 a buck converter with an arrangement (buck controller) to control a buck converter according to prior art,

FIG. 2 the design of a buck controller according to prior art,

FIG. 3 the design of a buck controller according to the invention,

FIG. 4 the signal behavior of a buck controller according to prior art, namely

• • a) the output voltage V_FB and the target value of said voltage (straight, continuous line)
  • b) the deviation, i.e., the difference of the output voltage V_FB from its target value after passing the analog-to-digital converter,
  • c) of the calculated and adjusted pulse width and
  • d) the target load current (straight line) in reference to the output current (serrated line) and the pulse width modulated pulse sequence PWM_H

FIG. 5 the signal behavior of an arrangement according to the invention (buck controller), namely

• • a) the output voltage V_FB and the target value of said voltage (straight, continuous line)
  • b) the deviation, i.e., the difference of the output voltage V_FB from its target value after passing the analog-to-digital converter,
  • c) of the calculated and adjusted pulse width and
  • d) the target load current (straight line) in reference to the output current (serrated line) and the pulse width modulated pulse sequence PWM_H

As shown in FIG. 1, in a buck converter 1 two switching transistors 2 and 3 are provided, each respectively switching alternating. Both transistors 2 and 3 are connected with their source-drain path in a current circuit between the input voltage V_IN and the ground. An inductivity 4 is connected therebetween, which is switched serially with a load resistor 5, over which the output voltage V_FBP−V_FBN drops. Parallel in reference to the load resistor a capacity 6 is switched.

During the period the first transistor 2 is switched on, namely the one located at the side of the input voltage, a load current flows through the inductivity 4 and through the load resistor 5. The second transistor 3 is blocked. During the period the first transistor 2 is switched off, the second transistor 3 is switched on. Now the energy stored in the inductivity 4 is drained. The current flows through the consumer 5, however now through the second transistor 3 and out of the capacity 6.

By modifying the switch on and switch off periods of the transistors 2 and 3 the output voltage can be adjusted and controlled by adjusting these periods using settings in turn influencing the output voltage. The regulation occurs in a known fashion by pulse width modulation (PWM) of the control pulses at the gates of the transistors 2 and 3.

The control of the transistors 2 and 3 occurs via a buck controller 7, which is controlled by a clock generator 8 and to which the output voltage V_FBP−V_FBN is returned as the control parameter.

As shown in FIG. 2, the output voltage V_FBP−V_FBN is applied to a first amplifier 9, with its output being applied to a difference amplifier 10. Here, the value of the target voltage is also applied, which is provided via a digital-to-analog converter 11 from a digital source, not shown in greater detail.

At the output of the difference amplifier 10 the deviation from the rule is then provided in an analog form. This is sampled via an analog-to-digital converter 12. This occurs according to prior art with the same frequency, by which also the pulse frequency occurs to control the transistors 2 and 3.

The digital value of the deviation at the output of the analog-to-digital converter 12 is then guided via a non-linear amplifier 13 and an IIR filter to a pulse width modulation circuit 15. This then represents the pulse width of the pulse sequence to control the transistors 2 and 3.

As shown in FIG. 4, the digital representation of the deviation according to FIG. 4b) is relatively coarse due to a considerable change of load at the load resistor 5. Using the same resolution, the size of the pulse width can then be determined, as shown in FIG. 4c).

As is apparent from FIG. 4d), this leads to considerable overshooting at the output of the buck converter 1 and to a visible delay at the transients in FIG. 4a)

FIG. 3 shows the solution according to the invention. Identical reference characters here indicate equivalent components of prior art.

According to FIG. 3 a sample clock generator 16 is provided, which controls the analog-to-digital converter 12 and all subsequent units with a higher clock than the clock generator 8. This oversampling leads to an essentially larger resolution of the deviation, such as shown in FIG. 5b). This way, the analog-to-digital converter 12 can sample the deviation n-times during the period length of the pulse sequence in order to control the transistors 2 and 3, for example 32 times per 2 μs length of period. The oversampling rate n can be programmed.

A moving average filter 12 is arranged downstream in reference to the analog-to-digital converter 17. Here, two moving average filter paths (not shown in greater detail) are implemented, with their reduction rates being programmable. Typically, a filter path is programmed for a reduction rate, which is equivalent to the oversampling rate. Another filter path is programmed, for example, to one-fourth of the oversampling rate. The higher reduction rate leads to a considerable restriction of the bandwidth of the sampled deviation signal. For this reason it is used during the steady-rate operation as is discernible in FIG. 5a) on the right side, in order to eliminate values that would couple noise into the return, particularly during the “rippling” of the output signal.

The filter path with the low reduction rate is used during load changes, such as is discernible in FIG. 5a) on the left side. It provides a greater bandwidth of the sampled deviation, which allows a quick reaction of the control circuit.

Within the moving average filter 17 a determination of a threshold being crossed is also included regarding the change of the speed of deviation. One or the other filter path is selected depending on a threshold being exceeded or fallen short of.

As shown in FIG. 3, a continuously adjustable pulse width modulation circuit 18 is provided. This way it is possible to adjust the pulse width of the pulse sequence also during the duty cycle.

As is apparent from FIG. 5, particularly from d), the control occurs after a change of load causing a considerable transient essentially faster and with much less overshooting.

In particular the ability for programming the parameters allows an easy adjustment to the different purposes for use.

LIST OF REFERENCE CHARACTERS

• 1 buck converter
• 2 first transistor
• 3 second transistor
• 4 inductivity
• 5 load resistance
• 6 capacity
• 7 buck controller
• 8 clock generator
• 9 first amplifier
• 10 difference amplifier
• 11 digital-to-analog converter
• 12 analog-to-digital converter
• 13 non-linear amplifier
• 14 IIR filter
• 15 pulse width modulation circuit
• 16 sample clock generator
• 17 moving average filter
• 18 continuously adjustable pulse width modulation circuit

Claims

1. A method for regulating a buck converter, comprising: adjusting amount of an output voltage at an input voltage via a controlled switching of an inductivity, switched serially with a load and over which the output voltage drops, using a pulse sequence showing a pulse rate and pulse width being modulated, wherein the output voltage is scanned with a sample rate, its value digitized, and used to adjust pulse width, adjusting the sample rate greater than the pulse rate and controlling the pulse rate of the impulse sequence during cycle duration.

2. A method according to claim 1, wherein the sample rate is adjusted to 2 to 100 times the pulse rate.

3. A method according to claim 2, wherein the sample rate is adjusted to 32 times the pulse rate.

4. A method according to one of claims 1 to 3, further comprising subjecting a digital signal generated by the sample rate to a digital reduction via filtering such that sample values are filtered out which are to be allocated to an integer multiple of sample frequency according to the sample rate.

5. A method according to claim 4, wherein the reduction occurs via a moving average filter, which shows several filter maxima at the integral multiples of the sample frequency.

6. A method according to claim 4 or 5, wherein the digital values are filtered with a programmable reduction rate.

7. A method according to claim 6, wherein the reduction with a first reduction rate is performed during the periods with essentially constant load, i.e., with a first transient, and with a second reduction rate during periods of load changes, i.e., with a second transient higher in reference to the first transient, with the second reduction rate being smaller than the first reduction rate.

8. An arrangement for regulating a buck converter comprising a control input for a pulse width modulated pulse sequence with a pulse rate and a voltage output, with the arrangement comprising a control input, which can be connected to the voltage output of the buck converter, and with a control output, which can be connected to the control input of the buck converter, and which comprises an analogue-to-digital converter between the control input and the control output, a non-lineal amplifier, an IIR filter, and a pulse width modulation circuit and a pulse rate clock generator being provided determining the pulse rate, wherein in a moving average filter is arranged between the analog-to-digital converter and the non-linear amplifier, a sample rate clock generator is arranged adjusting a higher sample rate with its sample rate analog-to-digital converter, moving average filter, non-linear amplifier, and IIR filter being controlled, the impulse rate clock generator being connected to the pulse width modulation circuit, and the pulse width modulation circuit being embodied continuously controlled in the pulse width, i.e., also during the duration of the pulse period.

9. An arrangement according to claim 8, wherein the moving average filter comprises two moving average filters with differently programmable reduction rates.