Patent Application
20200259027
The invention relates to a process for manufacturing all-silicon light-to-electricity converters with nanoscopic systems, in specific arrangements within the monocrystalline silicon to trigger a giant photoconversion.
This production process includes the nanoscopic modulation of silicon, and makes it possible to avoid the conflicts resulting from the successive manufacturing steps by superposition of the different phases of silicon transformation, while respecting adjusted geometric factors.
More particularly, the manufacturing process includes a local modification of the silicon crystal lattice into a new nanoscale arrangement to form a specific system, so as to improve the efficiency of the light-to-electricity conversion using the all-silicon converters. This involves the exploitation of the kinetic energy of hot electrons, which has become possible thanks to the mechanisms of the giant photoconversion (GPC, English acronym for Giant PhotoConversion); mainly, the low-energy generation and multiplication of secondary electrons.
The present invention relates and extends to the field of conversion of light energy into electricity, and in particular to all applications to light-to-electricity converters, photoelectric cells and photovoltaic solar cells with high efficiency. It involves in particular a process of manufacturing a new photovoltaic material, and photovoltaic devices using it having very high efficiency thanks to giant photoconversion.
The present production process utilizes photovoltaic industry equipment with two additional stations dedicated to specific operations implementing complementary processes for the manufacture of monocrystalline silicon photovoltaic cells.
The resulting converter can be used to form photovoltaic panels electrically connected in series or in parallel in appropriate circuits, as well as in the form of sheets, mats or mattresses.
The definitions below will be used throughout the following description.
Metamaterial: this term refers to an artificial material, in particular transformed crystalline silicon, having physical properties that go beyond the known, so-called natural properties. The metamaterial retains its original chemical composition. More specifically, it takes the form of at least one continuous or discontinuous layer, but also a field of beads or grains or various shapes, such as agglomerates or aggregates, which allows a low-energy generation and multiplication of secondary electrons, a specific electronic transport, an increased sensitivity to the intensity of light excitation, and a strong optical nonlinearity.
SEGTON: [Acronym for Secondary Electron Generation Tuned on Nanoscale] is a conditioned elemental unit of the crystalline lattice, characterized by its original system of electron energy levels, which is very well suited to the multistage conversion of light into electricity. SEGTON allows the low-energy generation and multiplication of secondary electrons that are additional to the primary photogeneration of the free carriers.
SEG-MATTER [acronym for Secondary Electron Generation-Matter] is a metamaterial, i.e., the specific crystalline material created in a single nanospace of the conjugated interactions: of structure, of doping, of electron transport and of strong physical fields for efficient light-to-electricity conversion, which contains homogeneously distributed elementary units called SEGTONS that form an ordered super-lattice immersed in a specific physical environment delimited by nanomembranes. A new crystallinity brings desired complementary functionalities on a nanometric scale.
More generally, this expression also refers to the production process for manufacturing the material capable of exploiting a set of energy levels of the SEGTONs.
Nanomembrane: it is a heterointerface or a surface (vertical, horizontal, parallel to the surface, more or less spherical or not) on which is made a change of the model of electron energy band, of conduction mode, and so on. This is, for example, the interface between two crystalline silicon phases: the SEG-MATTER and the surrounding untransformed natural silicon, which is characterized by the modification of the electron transport mode.
MTM: silicon-based metamaterial
a-Si: amorphized silicon
<a-Si>: amorphized phase of the silicon under mechanical stress
c-Si: crystalline silicon
<c- Si>: crystalline phase of the silicon under mechanical stress
Vacancy: point structural defect in a crystal lattice.
Divacancy: point structural defect in a crystalline lattice formed by two interconnected vacancies, forming a specific structural unit.
BSF: electric field at the back surface, i.e., an LH-type junction resulting from a gradual or abrupt modification of the density of doping impurities.
RIE: reactive ion etching.
LPCVD: low pressure chemical vapor deposition.
Amorphized nanoaggregates: amorphized aggregates or nanogroups of the locally transformed crystalline material, preferably silicon, which has been included by any suitable production process in the crystalline medium.
Inserted nanostructures: amorphized nanoaggregates, enveloped by a nanolayer of SEG-MATTER, i.e., of the metamaterial (MTM) capable of providing many secondary electrons resulting from collisions of hot electrons, optimally distributed within the converter, preferably the emitter.
GPC: Giant PhotoConversion—giant photoconversion allowing the optimal exploitation of the energy of the whole solar spectrum.
Currently, the manufacture of commercial photovoltaic devices is based on transformations of a semiconductor, for example doping with impurities, forming PN junctions, metallization, electronic passivation, anti-reflective arrangements.
The rather simple conventional architecture of a photovoltaic cell exploits natural materials that can only be modified to a limited extent. A very large proportion of the cells is designed as a semiconductor device with a single planar collection junction.
This vision can be enriched by the creation of dedicated sub-regions, subsystems, substructures, which complement on a nanometric scale the conventional design of the architecture of photovoltaic devices.
Years of multiple experiments have made it possible to implement methods of modulating the semiconductor material (mainly silicon) on a nanometric scale, so as to achieve new phenomena related to giant photoconversion.
The state of the art is widely illustrated and documented by the publication of prior patent applications filed in particular in the name of the company SEGTON AdT.
The adjustment of a light-to-electricity converter to a larger portion of the solar spectrum is complicated, on the one hand, because, for reasons of quantum mechanics, the conversion is efficient and optimal only in a very narrow spectral sub-band, and on the other hand, because the total solar spectrum is too large to allow efficient operations using devices with a single collection junction.
Two ways to proceed are available.
*Maintaining the same unique mechanism of photons/electrons interaction, most efficiently exploited in cells in “TANDEM” mode (for example, with various materials of the GaAs family), by creating a stack of cells having complementary band gaps, which make it possible to perform photoconversion over a larger solar spectral range than single-junction converters, but which, in return, are characterized by a much more difficult current collection as well as by problems with light concentration.
*Introducing additional mechanisms, such as, for example, low-energy generation and multiplication of secondary electrons, with its numerous coupled mechanisms such as specific functional separation (local transformations of the material, local electronic transport, and collection of photogenerated electrons).
The present invention relates to a process for manufacturing all-silicon converters having improved efficiency due to giant photoconversion thanks to their sub-regions, subsystems or substructures, such as, for example, a nanoscopic system of buried layers containing a silicon photovoltaic metamaterial. The manufacturing process leads to the device integrating the secondary low-energy generation and the multiplication of secondary electrons, with optimal collection of the photocarriers thus created.
The giant photoconversion represents a route to increase the efficiency of the conversion of light energy into electricity in devices with a single collection junction. The multiplication of low-energy electrons is the first mechanism in an indirect bandgap semiconductor, which has proved that silicon can be dramatically optimized in this way for the conversion of the solar spectrum into electricity.
The present invention is of particular importance because silicon, which largely dominates the photovoltaic industry (especially in its crystalline form), does not present resource problems given its abundance and ease of access in the earth's crust. Its extraction and its recycling do not pose significant problems of ecological nature, especially with regard to toxicity. In a way, the latest developments of silicon devices constituting giant photoconversion devices that are referred to in this invention represent a return to the first photovoltaic generation, and constitute excellent improvements of its founding concepts.
A conventional silicon photovoltaic cell production line can be quickly and cost-effectively transformed into a giant photoconversion cell production line.
The present innovative process is nano-technological in nature. It utilizes the means, equipment, and technologies implemented for silicon. It is particularly important to state that all these means and operations are now fully mature and well-developed.
The specific steps of the manufacturing process include a partial transformation of the crystalline silicon into an optimal nanoscopic arrangement to form a device that makes it possible to improve the efficiency of the light-to-electricity conversion. All the parameters, processes, procedures and steps in the manufacture of giant photoconversion devices have been tested and validated separately during the manufacturing of about twenty test series.
The first manufacturing step consists in producing a conventional single-junction crystalline silicon cell. Phosphorus, used as dopant, is diffused during this step into the silicon which was previously homogeneously pre-doped, for example, with boron, with a density of approximately 5.1015 per cubic centimeter.
The nanoscopic modulation is buried within the crystalline silicon by an amorphizing implantation followed by a post-implantation thermal treatment. The incident ion beam amorphizes the crystal lattice of silicon locally in a zone having predetermined thickness and depth (in the order of tens of nanometers) with high precision thanks to the physical properties of the process. The resulting amorphization has no technical utility as such, and imperatively requires an additional thermal treatment, which will result in controlled local recrystallization in the form of solid phase epitaxy.
The present invention utilizes, for the production of photovoltaic cells, industrial machines that are used individually in the field of microelectronics and optoelectronics. It should nevertheless be emphasized that microelectronic methods are not directly compatible as such with giant photoconversion manufacturing processes, at least because of the active surface of the device.
The objective of the production process presented here is to use as widely as possible existing equipment, validated methods, and existing photovoltaic product manufacturing sites, but also those initially set up for manufacturing operations in microelectronics, optoelectronics or micro- and nanotechnologies.
Virtually all equipment, tools, machines, machine sets, are normally available on the market, as well as production facilities dedicated to electronics, photovoltaics and microelectronics. All the manufacturing steps of giant photoconversion GPC photovoltaic cells can be performed on existing equipment with rather minor adaptations. Large-scale manufacturing can be performed using suitably adapted, and thus, significantly cheaper dedicated machines meeting the well-defined and restrictive conditions of mass production of the converters.
This invention relates to a process for the production of all-silicon light-to-electricity converters incorporating nanosystems conditioned in specific arrangements within a crystalline silicon wafer for an optoelectronic application, for example, for GPC.
The production process developed and verified in practice leads to a complete nanoscopic modulation of the crystalline material, while avoiding conflicts between the different successive manufacturing steps.
As has been shown previously, the most specific problem concerns the concatenation of operations, performed consecutively directly one after the other, because some of these operations exclude each other if the order is not correctly respected.
Several methods and operations are available, which are well known individually in the field of microelectronics, but cannot be applied as such in a complete manufacturing cycle of a giant photoconversion device. Generally, the effective solution requires an original sequence of known operations, which must be parameterized according to the specificities of the secondary generation converters.
The invention encompasses and contains the bases and the general process, which are exposed below in accordance with the succession of the main steps. The following is a short but complete descriptive list, presented as an example of the main manufacturing specifications adapted to a complete industrial manufacturing process.
Generally, the production process in small series of giant photoconversion devices is based on a multi-step treatment of silicon wafers. The number of these steps depends, among other things, on the initial state of the silicon wafers, which are supplied in a more or less preconditioned state.
Examples of a few main process steps are mentioned below:
Choice of the silicon wafer thickness: the thickness must be adapted to all the technological operations from a mechanical standpoint.
Surface: The first manufacturing steps concern the surface quality of the silicon wafer (RCA, microelectronic purification), cold polishing of the silicon wafer surface to free it from native oxide.
Sacrificial oxidation: so-called deep oxidation (at 100 nanometers) followed by etching of the initial oxidation (95 nanometers), with preservation of a SiO2 nanolayer (thickness of about 5 nanometers) as electronic passivation of the surface.
or total etching of the initial oxidation followed by 70 nm deposition serving as a nanolayer source of P2O5 diffusion, followed in turn by etching to a thickness of 5 nm.
Electronic passivation during manufacturing: preservation of a nanolayer (thickness of about 5 nanometers) of SiO2 or P2O5 after oxidation and diffusion, to protect the silicon surface during implantation.
Diffusion of donors: diffusion of phosphorus from the nanolayer source of P2O5 to establish a P profile and create an interface of the PN junction.
Protective masks: intermittent protection of the front and rear surfaces between successive technological operations.
Implantation: amorphizing implantation of ions through protective surface nanolayers (thickness of about 5 nanometers), with a requirement of excellent geometric planarity characteristics.
Implantation masks: for discontinuous amorphization operations, corresponding to patterns of buried substructures.
Thermal treatment: annealing adapted to the regime of admissible temperatures corresponding to the deposition of the thermal energy required to modulate the transformed material through a solid phase epitaxy.
Conditioning of SEGTONs and SEG-MATTER: slowed-down solid phase epitaxy ensuring the calibration of active subsystems.
Underground substructures: Active subsystems inserted in the emitter according to the confirmed converter architecture.
Electronic passivations: passivation and electronic protection layers deposited after the conditioning processes of the SEGTONs and SEG-MATTER.
Rear surface: creating an acceptor profile (B) by diffusion or by implantation to form a BSF (English acronym for Back Surface Field); electronic passivation; rear mirror; contact grid.
Rear mirror: system of SiO2/Al layers on the rear face for optical trapping.
Annealing and contact conditioning.
In the following, a few selected examples of the entire manufacturing process are described in correctly arranged sequences of operations, which are already known individually, especially in microelectronics, but must be parameterized according to the specificities of a production cycle of a giant photoconversion device.
9.1 Pre-Doped Silicon Wafer, Preferentially with Boron
*Monocrystalline silicon wafer CZOCHRALSKI-CZ-Si or with FZ-Si float zone.
*Phosphorus (P) doping, preferentially in the order of 1018 per cubic centimeter, with boron (B) pre-doping at usual concentration in the order of 1015 per cubic centimeter.
*Front and rear face cleaned, but not necessarily polished.
*Crystalline orientation <100>.
*RCA bath in a chemical cleaning station.
*Cleaning by sacrificial thermal oxidation at a temperature of 850° C. for approximately 2 hours leading to a sacrificial SiO2 layer having a thickness of from 50 to 100 nanometers.
In an oxygen ion diffusion oven.
*By implantations of boron ions with a relatively low energy at a few degrees of offset angle with respect to the vertical, to avoid ion channeling.
*The penetration depth comes from the implantation energy, which is precisely determined by simulations using software like SRIM/TRIM; for example, 25 keV through a SiO2 passivation layer having a thickness of 100 nanometers, with the dose: 5−10×1014 per square centimeter.
9.5 Front Face Formation, n-Type Doping Diffusion
*Etching of the protective SiO2 passivation layer.
*Deposition of the surface source of phosphorus diffusion, for example, a nanolayer of P2O5.
*Diffusion at so-called low temperature (<1000° C.) of phosphorus from the surface source.
*Formation of the PN junction and of the emitter.
*Etching of the P2O5 diffusion source layer to 5 nanometers thick to form a protective nanolayer.
*Implantation of phosphorus ions through the protective P2O5 nanolayer, with an offset angle of a few degrees relative to the vertical, to avoid ion channeling.
*The implantation depth depends on the implantation energy, determined by simulation, using a numerical code, for example SRIM/TRIM.
*Amorphizing implantation energy: 30-200 keV.
*The implantation dose is established below 1015 ions per square centimeter.
*First thermal treatment applied to reduce the thickness of the amorphized nanolayers and reciprocally dilute amorphized inclusions in the crystalline phase and crystalline inclusions in the amorphized phase within the amorphized-crystalline phase transition zone.
*Annealing thermal cycle—formation and conditioning of buried substructures composed of amorphizations and of systems of transformed and specifically structured crystalline Si nanolayers.
Note: The post-implantation thermal treatment that follows a so-called direct amorphization is significantly simplified and has an improved thermal budget particularly suitable for serial mass production.
According to this thermal treatment, the annealing temperatures are up to 700° C., which proves particularly favorable for the neutralization or heal of practically all extensive post-implantation structural defects, in order to obtain a more efficient material.
For example, the process is carried out in the same way by adjusting the annealing temperature and the thermal cycle to the quality of amorphization.
*Objective: remove the protective SiO2 passivation layer (100 nanometers) according to a pattern to allow metallization by inductively coupled plasma etching (RIE).
*Chemical etching.
*A 5-nanometer thin layer is always preserved to protect the surface of the semiconductor; instead of SiO2, it is possible to use the P2O5 that remains after the phosphorus diffusion process.
*Objective: embed discontinuous amorphized substructures by amorphizing implantations through an implantation mask with different patterns and geometries according to the requirements imposed by the electronic transport.
*Conventional realization with a photolithographic mask and illumination by a mercury vapor lamp.
*The operation has many intermediate steps using masks with different patterns.
*Covering with photoresist to protect the lower and upper faces in an intermediate manner.
*Exposure to light: all the reactions mentioned above are induced by light.
*Chemical processes: removal of fragments according to the selected patterns.
The conventional amorphization using a focused ion beam scanning the surface of the Si wafer inevitably introduces numerous structural defects. As such, this operation is not usable for the industrial manufacture of converters with secondary generation. The disqualifying aspects can be summarized as follows: poor control of the modulation of the material during the local impact of the ion beam and, consequently, of its post-implantation annealing; exaggerated requirements regarding the thickness of the initial amorphization to keep sufficient room for performing the healing recrystallization; severe limitations on the design and architecture of the converter because of the location of sub-structures buried within the crystal lattice; obstructions to electron transport around the nanostructures buried within damaged material; complications concerning the collection of both secondary and primary charge carriers.
It is known to persons skilled in the art that a post-implantation thermal treatment heals a few types of structural defects. For reasons imposed by the conditions of manufacture and the packaging of the SEG-MATTER, this treatment is performed in a well-delimited range of suitable temperatures and with a reasonable thermal budget from the manufacturing standpoint.
There are various combinations that lead to the emitter structure of the GPC converter using diffusion and/or implantations of doping impurities.
In the first case (phosphorus implantations), both the dopant profile and the front surface electric field (FSF), as well as the modification of the crystalline structure, are the result of ion implantations (preferably phosphorus with regard to amorphization).
In the second case (diffusion of doping impurities), the profile of the dopant is made by diffusion (preferably phosphorus), while the modification of the crystalline structure is the result of ion implantation (preferably phosphorus or silicon).
The modification of the crystalline structure compliant with industrial requirements should be:
*Made by an ion implanter with wide defocused beam, securely stable and homogeneous, ensuring industrially useful amorphization (direct amorphization).
*Implantation of phosphorus or silicon made with energies of 80-180 keV and with a density of 6 to 10×1014 ions per square centimeter.
*In the case where the phosphorus diffusion has been made beforehand, in order to obtain buried amorphization, silicon ions can be implanted instead of phosphorus ions.
The low thermal budget treatment is substantially shorter than 30 minutes at a temperature of about 500° C. in a tray oven, followed by progressive cooling. In some special cases, a short-sequence thermal cycle is possible.
A superposition of the effects of optical confinement (Si02/Al mirror) and of collection at the rear face by a comb combined with a full-surface contact in aluminum.
This concerns, for example, multilayer grid metallization: titanium/palladium/silver.
Objective of the LPCVD: complement the basic SiO2 layer having a thickness of 5 nanometers by a complete protection SiO2 layer of about 100 nanometers (to ensure an efficacious electronic passivation). It is made, for example, in a tube of a suitable material, brought to and stabilized at 420° C. for 20 minutes; the deposition process lasts 5 minutes.
Objective of the cathode sputtering: complement the SiO2 protection layer of about 5 nanometers by a layer of SiO2 of 100 nanometers (to ensure an efficacious electronic passivation):
*The operation is performed at room temperature
*The pressure is 2×10−3 mb
*The power is 200 W
*The distance to the targeted silicon wafer is 100 nanometers
*The duration of the operation is in the order of 13 minutes
The number of processing steps depends inter alia on the initial state of the purchased silicon wafers. The main manufacturing steps concern:
Surface: the required surface quality of the silicon wafer can be obtained by RCA treatment, microelectronic purification, cold polishing to free it from native oxide.
Thickness of the silicon wafer: must be adapted to all the subsequent technological operations.
Sacrificial oxidation: deep oxidation (at 100 nanometers), etching of the initial oxidation (95 nanometers), preservation of a nanolayer as protective nanolayer (thickness of about 5 nanometers) or of the pure silicon surface itself, ready for a P2O5 deposit as the nanolayer source of P diffusion.
Protective masks: protected surface between successive operations, as well as amorphizing implantation masks corresponding to substructure patterns.
Back surface: p-type profile, B acceptor profile by diffusion or implantation, BSF, passivation, rear mirror, contact grid. Front surface: n-type profile, P donor profile by diffusion from the source in the form of a P2O5 nanolayer, PN junction interface.
Buried substructures: active substructures inserted into the emitter and having excellent geometric planarity characteristics, concept of the particular converter architecture.
Implantation: implantation of ions through the protective nanolayer (thickness of about 5 nanometers).
Thermal treatment: adapted deposition of thermal energy to modulate and condition the transformed material.
Conditioning of SEGTON and SEG-MATTER: solid phase epitaxy with calibration of the active subsystems in their environment.
Rear mirror: Rear mirror of SiO2/Al on the rear face for optical trapping. Contacts activation annealing.
11. Production Process in Small Series of Giant Photoconversion Devices—Insertion of the Nanoscopic Systems into Silicon Wafers—Example of a Cycle with Non-Mutually Exclusive Sequences
Example of operations leading to the insertion of nanoscopic systems in an all-silicon light-to-electricity giant photoconversion device; main steps and their characteristics:
*silicon used: CZ or FZ silicon wafer having a <100> crystallographic orientation,
*thickness of the silicon wafer used: approximately 150-500 micrometers,
*diameter of the silicon wafer used: 4, 6 or 12 inches,
*p-type pre-doping: homogeneous density of boron with a density of about Na˜1-5.1015 cm−2—the operation must leave the maximum useful lifetime of minority carriers in the base of the converter (avoiding activation of unintentional impurities and defects),
*sacrificial oxidation of 50 nanometers at a temperature below 100° C.,
*first implantation (BSF) on the rear face with boron, at a density of 1015 cm−2, with a maximum density profile at the surface/interface, except in the alignment zone (using the mask of the metal rear grid),
*etching of the SiO2 from the front face, using HF buffer, except in the alignment zone,
*pre-deposition on the front face of a phosphorus source to carry out n-type doping by diffusion,
*the low-temperature diffusion profile is determined in a predictive manner by a simulation software, for example, ATHENA (registered trademark),
*second implantation of phosphorus on the front face, energy: 50-180 keV, dose 8.1014 cm−2, except on the alignment zone (using the implantation masks),
*thermal treatment cycle determined predictively by a simulation code,
*partial etching by chemical stripping of the SiO2 on the rear face, respecting the pattern of the contact fingers using a mask,
*metallization of the rear face with a 1-micron aluminum layer,
*etching of the alignment pattern on the rear face (one mask for the alignment),
*slow etching of the SiO2 layer on the front face using HF:H2O,
*three-layer metallization of the front face grid: Ti/Pd/Ag,
*etching of the metallized layer of the upper face in the alignment zone (two masks for the alignment),
*infrared alignment,
*etching of the metallized layer of the front face (mask of the front face grid).
A: Implantation, Amorphization and n-Type Doping Using Phosphorus Ions—Example of a Cycle with Non-Mutually Exclusive Sequences
An exemplary solution of the process based solely on ion implantations, characterized by the following steps:
1) RCA cleaning.
2) Thermal oxidation 1000 Å.
3) Implantation No. 1: boron through the rear face and the thermal oxide 1000 Å.
4) Resin deposition on the rear face.
5) Photolithography of the rear face and calibration figure (mask 1).
6) Thinning of the front panel, to 50 Å.
7) Removal of the resin protection on the rear face.
8) Implantation mask applied onto a layer of polysilicon having a thickness of 0.2 micrometers.
9) Photolithography of different fingers with different spacings on polysilicon (100, 200 micrometers, all having an identical width of 500 micrometers (mask 6).
10) Implantation No. 2: implantation of amorphizing phosphorus in channel 0. 180 keV, 7.1014 At/cm2.
11) Total removal of the polysilicon.
12) Implantation No. 3 with an overdoping profile; phosphorus is used for the channel of the front face, with the following characteristics: 0.25 keV, 7.1014 At/cm2.
13) Post-implantation thermal treatment.
14) Treatment of two sets of silicon wafers in a “perfect” parallel diffusion mode.
15) Intermediate protection of the front face.
16) Photolithographic etching of the grid finger on the rear face.
17) Photolithographic etching of the 1000-Å SiO2 contact finger.
18) Removal of the protective resin from the front face.
19) Total treatment of the rear face of the silicon wafer with a 2-micrometer aluminum deposit.
20) Resin protection of the rear face.
21) Photolithography of the front face comb (mask 3).
22) Lithography of the comb by etching 50 Å of SiO2.
23) Removing the resin protection from the rear face.
24) Etching the contacts (mask 4) for removal.
25) Deposition of a double layer Ti/Au—150 microns/1 micron.
26) Removal by lifting (lift-off).
27) Deposition of SiO2 by CVD or cathode sputtering on the front face.
28) Protection of the rear face with resin.
29) Photolithographic etching of the front face contact (mask 5).
30) Oxide-assisted photolithographic etching of the front face contact.
31) Removal of the protective resin on the rear face.
32) Annealing of the contacts under N2H2 atmosphere for characterization during treatment.
33) Protection with resin on the front face for cutting.
34) Cutting the cell on the silicon wafer by sticking it on blue adhesive tape.
B: n-Type Doping Using Phosphorus Diffusion, Amorphizing Implantation Using Phosphorus Ions—Example of a Cycle with Non-Mutually Exclusive Sequences
An exemplary solution of the process based on diffusion and implantation of ions, characterized by the following steps:
1) RCA cleaning.
2) Thermal oxidation 1000 Å.
3) Implantation No. 1: boron on the rear face through the 1000-Å thermal oxide layer.
4) Protection of the rear face with resin.
5) Lithographic etching of the active zone and of the calibration figure of the front face (mask 1).
6) Total removal of SiO2.
7) Removal of the protective resin on the front face.
8) Deposition of the P2O5 oxide by diffusion source and use of a passivation layer.
9) P diffusion.
10) Thinning of the P oxide on the front face.
11) Annealing of the diffused P.
12) Implantation mask, deposition of a layer of polysilicon having a thickness of 0.2 micrometers.
13) Photolithographic etching of the polysilicon: several spacings between fingers 100, 200, 500 micrometers. They all have the same width of 500 nanometers (mask 6).
14) Amorphizing implantation with phosphorus on the front face in a channel at 0 degree angle with 180 keV and 7.1014 At/cm2.
15) Total removal of the polysilicon.
16) Annealing after implantation.
The thermal oxidation of the GPC cell can be carried out in an oxidation oven, exploited in microelectronics, reaching 1000° C. under N2, O2, H2, HCl and forming an oxide layer having a thickness of 0.5 to 1.6 μm.
Implantation characteristics with focused beam require a beam current of from 3 microamperes to 2 milliamperes, the acceleration voltage ranging from 5 to 200 kV, up to 125 atomic mass, with the ability to process silicon wafer samples having diameters ranging from 1 cm2 to 6 inches.
The creation of an intrinsic electrostatic field on the front face of the silicon wafer to manufacture a GPC cell can be performed using shallow implantation of phosphorus ions (depth <1.0 μm). This second implantation of the GPC cell can be done with the same ion implanter operating in the lower energy range forming the shallow impurity profile.
The first annealing of the GPC cell at about 500° C. should generally be followed by the second annealing operation which is cyclical with heating and cooling steps. The cycle can be performed in the same oven as that used for the first annealing step.
The initial values for the equipment selected for manufacturing were obtained with the CAD software CAM, which provides adjustment data at the beginning of the iterative process for the micro-manufacturing machine with a margin of error reduced by specificities of the metamaterial manufacturing and by adequate machinery.
19. Production Process in Small Series of Giant Photoconversion Devices—Examples of Nanoscopic Transformations of Crystalline Silicon into an Optimal Arrangement to Form Buried Active Subsystems
The manufacturing process according to this invention constitutes a nanoscopic transformation of crystalline silicon into an optimal arrangement to form subsystems buried in the crystal lattice that make it possible to improve the efficiency of light-to-electricity conversion. All parameters, procedures and manufacturing steps of the GPC have been tested and validated separately and in combination during the manufacture of many test series.
To be useful in terms of light-to-electricity conversion, silicon must undergo a complex transformation that will shift from the structural defects being normally distributed in a rare, random and scattered manner to a structure composed of elementary units called SEGTONS of the ordered super-lattice, thus forming a metamaterial called SEG-MATTER. The most important aspects concern the nature, density and number of point defects properly positioned within the converter space.
To perform its functions, the nanolayer of metamaterial is integrated into a material (preferably crystalline silicon, c-Si), properly doped by n-type doping. This layer is bounded by two planar interfaces (nanomembranes) delimiting it according to an earlier invention.
The thickness of the metamaterial nanolayer (<c-Si>nanolayer) and the density of the grafted SEGTONs are self-controlled during manufacturing by the local mechanical stress (coming from dilatations between a-Si and c-Si), which are induced by, and result from, recrystallization cycles (solid phase epitaxy) occurring at suitable temperatures. Experiments (X-rays, LEED) show that on the side of the crystalline phase (well visible by available techniques), the final thickness of the nanolayer SEG-MATTER is in the order of 5 to 10 nanometers.
Keeping in mind all the individual steps, they are integrated into a single and complete industrial-type manufacturing process. As a result, the main features related to the SEG-MATTER concern:
a deep local transformation of the semiconductors (preferably c-Si), possible on a nanometric scale, which leads to a crystalline silicon metamaterial called SEG-MATTER,
a high density (1020 cm−3) of the SEGTONs in the metamaterial, with a homogeneous distribution,
uniform and stabilized composition of the SEG-MATTER nanolayers,
sufficient quantities of all metamaterial nanolayers corresponding to the intensity of the incident photon flux,
adapted spatial position of the SEG-MATTER system, which must be close to the place where there is the absorption of energetic photons (spatial optimization):
*proximity and/or unity of the absorption zone and secondary generation zones;
*maximum and optimized exposure surface (shapes and arrangements) for collision interactions with hot electrons.
The metamaterial nanolayer is designed to withstand and remain after treatments carried out at unusually relatively high temperatures (450-550° C. and 250-450° C.) for the divacancies, because of the maintenance of the local mechanical stress. This characteristic differs from the fact, well-known to persons skilled in the art that the divacancies recombine at temperatures below 250° C.
The most specific problems concern the concatenation of operations that follow each other consecutively, since some are mutually exclusive. For example, in the present invention, the temperatures of the successive procedures in the production cycle necessarily range stepwise from the highest toward the lowest, while respecting each of the steps described above.
Light-to-electricity converters containing the substructures (continuous or discontinuous) in the emitter have been described previously. One of the most important elements of the dedicated subregion, sub-system and substructure is a component that is artificial on a nanometric scale and that should be able to complement the conventional conversion with an improvement due to the new mechanisms.
This is ensured by an artificial material (SEG-MATTER), formed inter alia from well-defined building units, having a well-defined density and localized in a well-defined manner in the well-determined volume of the converter. To ensure the complete functionality of the conversion of the SEGTONs and of the SEG-MATTER, a number of strict conditions must be met.
Generally, the solution requires specific sequences of known operations, which must be parameterized according to the physical and technological features of the process.
The manufacture of a GPC device requires the integration of a series of operations that are, on the one hand, well known in the photovoltaic and microelectronic technologies (operations, procedures, machines), but on the other hand, cannot to be applied as they are, because of their specific conditions related to the large active surfaces of the devices.
Manufacturing can be carried out using existing equipment with a few minor adaptations. Virtually all necessary machinery and tools have been tested and are normally available in the industry. The future large-scale manufacturing will be operational on dedicated, simpler, and significantly less expensive production machines.
For example, the structure of a test device contains an electronic passivation SiO2 carried out by a low pressure vapor deposition method. The passivation layer has a thickness of 100 nanometers. The crystalline silicon doped with phosphorus has a thickness equal or lower than 170 nanometers, the layer strongly doped with amorphized silicon has a thickness of 20 nanometers, the PN junction is 1 micron below the surface (this value is not highly constraining). The amorphized layer is swollen, causing mechanical stress due to the discrepancy between the crystalline lattice and the amorphization.
The rear face contact can be made of aluminum and the front face electrodes can be made of silver or metal tri-layer.
The main originality of the invented manufacturing technology lies in the range of specific operations, as compared to the usual technology of crystalline Si cells, and in the organization of the manufacturing steps. The main constraints come from the fact that GPC sub-structures cannot be heated above 500° C.
Once the metamaterial layer has been manufactured, to create the passivation layer without heating too much, one must use chemical vapor deposition, which can be carried out at low temperature (which is not the case for thermal oxidation). Thus, the best way to proceed is to use a compromise:
firstly, perform a first thermal oxidation,
then, thin the Sift layer by etching to 5 nanometers,
create the nanostructured layer by wide defocused beam ion implantation,
adjust the nanolayer system by annealing cycles,
return to electronic passivation to increase its thickness by chemical deposition.
*material: CZ or FZ silicon in the form of wafers with a <100> crystallographic orientation,
*homogeneous density p-type pre-doping with boron of 1 to 5.1015 At per cubic centimeter,
*the useful lifetime of the minority carriers must be as long as possible (it depends on quality),
*diameter and thickness of the silicon wafer: 4, 6 or 12 inches, thickness 150-500 micrometers,
*thickness of the initial sacrificial oxidation layer expanded at a temperature below 1000° C.,
*first implantation at the rear face, with boron: 1015 At/cm2, leading to a profile having its maximum on the surface except on the alignment zone,
*etching of the SiO2 from the front face with HF buffer, except on the alignment zone,
*pre-deposition of a source of phosphorus diffusion on the front face,
*diffusion according to a profile determined by the prior simulation performed with the software, for example, ATHENA,
*second implantation of phosphorus on the front face, energy 180 keV, dose 8×1014 At/cm2, except on the alignment zone; “direct” amorphization.
*Partial etching of SiO2 of the rear face, respecting the pattern of the contact fingers,
*metallization of the rear face; deposition of a 1-nm Al layer,
*etching of the rear face according to the alignment patterns (possibly with mask),
*Slow etching of the SiO2 of the front face with HF:H2O,
*Tri-layer metallization of the front face: Ti/Pd/Ag,
*etching of the metal of the face according to the pattern of the contact zone.
20. Machines that can be Used as References to Implement the Production Process According to the Present Invention
The following list is a non-exhaustive example.
Machine for the reactive ion etching of the silicon wafer: inductively coupled plasma etching machines, for example the machine AVI21 TEC OMEGA 201 with RF inductive power of 600 W (13.56 MHz), RF clamping power of 600 W (13.56 MHZ), treatment temperature of from 10 to 20 degrees Celsius, and the possibility of using the following gases: SF6, CF4, O2, CHF3, AR, with cooling of the rear face of the GPC by helium;
Standard production photolithography equipment (standard workshop mask as instruments), which is only necessary in the case of a GPC with discontinuous substructures. The alignment mask is an example of the necessary instruments;
Ion implanter for the second treatment of the GPC cell;
Second annealing step for the GPC cell: oven identical to that used for the first annealing step with rapid temperature variation controllable by computer;
Cathode sputtering machine for the metallization of the rear contacts of the GPC cell, such as, for example, UNIVEX 450C, where the metal can be aluminum, the RF or DC power and the required vacuum limit being 1.10−7 torr;
VARIAN 3 6 16 machine for the metallization of the front contacts of the GPC cell with titanium, palladium or silver using an electron gun for evaporation, with a power of 6 kW, a cryogenic pump, and a minimum pressure of 5.10−7 bar;
Instrument for the creation of a 100-nanometer protective SiO2 layer for the passivation of the GPC cell by an LPCVD oven, such as LPCVD6, whose characteristics are: maximum temperature 580° C., length of the tray area 50 cm, gas: N2, NH3, SiH4, SiH2Cl2, N2O;
Cathode sputtering machine for sputtering SiO2 or ITO on the GPC cell, such as the ALCATEL 600, with a cryogenic pump, an RF or DC power source, and a pressure of 10−7 ton;
Machine for the final cleaning of the GPC cell for microelectronic circuits with class 100 atmospheric control, nitrogen dryers using ion-free water, a resistivity measurement function to measure the quality of the drying and cleaning between the different baths, the vapors being extracted from the bottom at the top of the device.
The present invention is naturally not limited to the embodiments described and shown but covers all variants, alternatives or changes that can be made or their equivalents used without departing from the spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 1700583 | Jun 2017 | FR | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/FR2018/000155 | 6/4/2018 | WO | 00 |
