Patent Application
20080228988
Electronic data processing systems, such as computer systems typically include one or more memory arrangements for storing data. An example memory arrangement includes one or more data busses adapted to transmit data.
One embodiment provides a method of transmitting configuration data in a memory arrangement. The method includes controlling, with a control unit of the memory arrangement, data transmissions via a configuration data bus in the memory arrangement, the controlling including controlling transmitting configuration data of the memory arrangement for storing in at least two register units of the memory arrangement via the configuration data bus from the control unit to each of the at least two register units. The method includes storing, in the at least two register units, the configuration data. The at least two register units have a same bus address identifying the at least two register units on the configuration data bus. The method includes requesting, with the control unit, configuration data stored in the at least two register units. The method includes transmitting, under control of the control unit, the stored configuration data via the configuration data bus from only one of the at least two register units to the control unit.
The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
In the following, exemplary embodiments of the present invention will be described in detail. It is to be understood that the following description is given only for the purpose of illustrating the principles of the invention and is not to be taken in a limiting sense. Rather, the scope of the invention is defined only by the appended claims and is not intended to be limited by the exemplary embodiments described hereinafter.
It is also to be understood that, in the following detailed description of the exemplary embodiments, any direct connection or coupling between functional blocks, devices, components, or other physical or functional units illustrated in the drawings or described herein could also be implemented by an indirect connection or coupling.
It is further to the understood that the features of various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
The present invention generally relates to the field of memory arrangements and, in particular, to memory arrangements used in data processing devices, for example in computer systems. Particularly, the present invention relates to memory arrangements comprising configurable settings adapting the memory arrangement to specific parameters of the environment the memory arrangement is used in. These settings or configuration data may comprise for example timing parameters, address mappings, address offsets, address ranges, the use of error detecting and correcting means, or protocol characteristics of a protocol used between the memory arrangement and the data processing unit. Moreover, this may comprise also special settings for test and analysis of the memory arrangement.
A example first type of configuration data relates to the memory arrangement 100 as a whole and is used by the memory arrangement 100 within one specific circuit part only. Configuration data like this may comprise for example timing and protocol characteristics of an interface between the memory arrangement 100 and the data processing unit the memory arrangement is connected to. Register units for storing this type of configuration data are for example register units 117-122 in
An example second type of configuration data may comprise configuration data which is configurable independently for each of the data banks 101-104. This may comprise for example address mapping or address offset configurations for the memory banks 101-104. To achieve short connections between these register units and the corresponding memory banks the configuration data register units containing these configuration data are placed in the embodiment illustrated in
A third example type of configuration data is configurable once for the memory arrangement 100 as a whole, but is used at several locations inside the memory arrangement 100, for example for configuring the timing characteristics of the memory banks 101-104. Therefore, this configuration data is stored nearby each of the memory banks 101-104. In the embodiment illustrated in
The register units 105-122 are connected to a configuration data bus 123 and a control unit 124 of the memory arrangement 100 controlling transmissions on the configuration data bus 123 is also connected to the configuration data bus 123. A configuration data bus 123 may comprise address lines for addressing the register units 105-122, data lines for transmitting data between the register units 105-122 and the control unit 124, and control lines, for example a read enable line and a write enable line, for controlling the data flow on the configuration data bus 123. Each register unit 105-122 comprises an address for identifying the register unit on the configuration data bus 123.
When configuration data is written from the control unit 124 to one of the register units 105-122, the control unit outputs the address of the register unit to be provided with configuration data on the address lines of the data bus 123, outputs the configuration data to be written into the addressed register unit on the data lines of the data bus 123 and asserts the write enable line of the data bus 123. Upon assertion of the write enable line, each register unit 105-122 compares the address provided on the address lines of the data bus 123 with their own address and, in the case of a match between the address on the data bus 123 and the own address, the configuration data provided on the data lines of the data bus 123 is stored in the register unit having the matching address.
When retrieving data from the register units 105-122 to the control unit 124, the control unit 124 outputs the address of the register unit of which the configuration is to be retrieved, and asserts the read enable line of the data bus 123. Upon assertion of the read enable line the register units 105-122 compare the address on the address lines of the data bus 123 with their own address and output in the case of a match between the address on the address lines of data bus 123 and the own address of the register units the configuration data on the data lines of the configuration data bus 123. Control unit 124 receives the configuration data from the data lines of the configuration data bus 123 and the read operation is completed.
As illustrated in
In operation, the data processing unit 128 communicates with the memory arrangement 100 via the data interface 129 for storing data in the memory banks 101-104 of the memory arrangement 100 and for retrieving data from the memory banks 101-104 from the memory arrangement 100. The memory arrangement configuration device 126 configures the memory arrangement 100 according to the need of the data processing system 127. This configuration may comprise the setting of timing characteristics, address ranges, and communication parameters of the memory arrangement 100. As described above, this configuration data may comprise configuration data of the third type, which means configuration data that is common for the memory arrangement 100 as a whole, but is to be configured at several locations, (i.e., several register units) due to the internal structure of the memory arrangement 100. This may comprise for example the configuration of register units 113-116 of
The configuration data bus structure 130 comprises a control unit 124, three register units 112-114, a configuration data bus 123, and a connecting unit control unit 131. The data bus 123 comprises a data line comprising two data line portions 132 and 133 and a data line connecting unit 134 arranged between the data line portions 132, 133. The data bus 123 comprises further address lines 135 for addressing the register units 112-114, a read enable line 136 for signaling a read operating on the configuration data bus 123, and a write enable line 137 for signaling a write operation on the data bus 123. The connecting unit 134 comprises a connecting mechanism configured to connect or disconnect the data line portions 132, 133, wherein the data line connecting unit 134 is controlled by the connecting unit control unit 131. In the embodiment illustrated in
Assuming that register units 113 and 114 share the same configuration data bus address, for example “address A”, for setting a configuration data value simultaneously within one write operation at both register units 113 and 114, and register unit 112 has a different address, for example “address B”, the operation of one embodiment of the configuration data bus structure 130 is as follows.
When writing configuration data from control unit 124 to address A accessing register units 113 and 114, the control unit 124 outputs address A on the address lines 135, the configuration data value to be written on the first data line portion 132, and a write enable signal on the write enable line 137. Connection unit control unit 131 is connected to the read enable line and monitors the read enable line for sending a signal to the connection unit 134 for disconnecting the connected data line portions 132, 133 in the case of a read enable signal. As there is no read enable signal on line 136, the connection control unit 131 does not detect a read enable signal and therefore connection unit 134 connects data line portion 132 to data line portion 133 passing the configuration data from the control unit 124 via the second data line portion 133 to register unit 114. Upon receiving the write enable signal each of the register units 112-114 compares the address on address lines 135 with their own address and, in the case of a match, the configuration data of the data line portions 132 and 133 are stored in the respective register units.
In this case, register units 113 and 114 detect a match between the address received on the address lines 135 and therefore the configuration data value sent from the control unit 124 is stored in each of the register units 113, 114.
In case control unit 124 addresses configuration data bus address B, the same operation takes place, except for the fact that register unit 112 stores the configuration data received via data line portion 132 instead of register units 113 and 114.
In the case of a read request to address A, the control unit 124 outputs address A on the address lines 135 and activates the read enable line 136. Upon activation of the read enable line 136 the connection unit control unit 131 controls the connection unit 134 such that connection unit 134 disconnects data line portion 132 from data line portion 133. Furthermore, upon reception of the read enable signal on read enable line 136, each of the register units 112-114 compares the address sent on the address lines 135 with their own address and outputs its configuration data value upon a match of these addresses to the data line portions it is connected to (i.e., in the present case of address A an output of configuration data of register unit 113 to data line portion 132 and an output of register unit 114 to data line portion 133). As connection unit 134 disconnects data line portions 132 and 133, only the configuration data output of register unit 113 is transmitted to the control unit 124. This can avoid glitches on the data lines due to asynchronous outputs of the register units 113 and 114 and can avoid malfunctions due to shortcuts on the data lines.
A read operation request to address B is performed in the same way as stated above, wherein in this case register unit 112 outputs the requested data to data line portion 132 and the connection state of connection unit 134 does not matter in this case.
In
In one embodiment, assuming that register units 113-116 have address A as the address for identifying the register units on the configuration data bus, a write operation of control unit 124 addresses all four register units 113-116 at the same time. Connection units 134, 138, and 139 are controlled such that during write operation the data line portions of configuration data bus 123 are all connected to control unit 124. Therefore, a write operation to address A sets configuration data in the register units 113-116 at the same time. When requesting configuration data from address A, connection units 134, 138, and 139 are controlled in such a way that only the data line portion connected to register unit 113 is connected to the data line portion connected to the control unit 124. Thus, when requesting data from register units having address A, only configuration data of register unit 113 is forwarded to control unit 124, thus avoiding bus contentions from occurring on the data lines caused by asynchronous outputs on the same data lines from register units 113-116. As the remaining register units 105-112 and 117-122 are uniquely addressed on the configuration data bus 123, during addressing these registers, connection units 134, 138, and 139 do not disconnect data line portions of the configuration data bus 123.
Furthermore, the connection unit control unit 131 may comprise a request control register unit configurable to determine which of the register units 113-116 having the same address shall be connected through to the control unit 124 in case of a read access to these register units. With the help of such a configuration it is possible to verify the correct setting of each of the register units 113-116 during, for example, a manufacturing test of the memory arrangement.
The configuration data bus structure 130 embodiment of
The data interface 129 may be configured to allow a transmission of read, write, address, and command data in the form of data packets according to a predefined protocol. This data protocol may also be configured to allow a transmission of data for configuring the timing characteristics, configuration data as described above, and test data of the memory arrangement. A fast read out of these data via the couplers 141, 142 to the data interface 129 may be possible to speed up testing the memory arrangement during a manufacturing test. Furthermore, the data communication via data interface 129 and coupler 141, 142 may also be bidirectional to further increase the transmission speed of data during, for example, a manufacturing test.
In one embodiment, access control register 147 is accessible via the configuration data bus 123 like a regular register unit, for example register unit 112 of
In one embodiment, an access mechanism like this provides for a manufacturer of a semiconductor memory chip the possibility to realize an arbitrary number of register units for test and configuration purposes that can be hidden and made unaccessible to the end customer, and allows these register units to be accessible only to those that know the certain predetermined value that has to be written into the access control unit 147 for accessing these hidden register units. Additionally, this provides an easy and inexpensive way of realizing such hidden register units, when a configuration data bus structure, such as illustrated in
In one embodiment, after a reset of the memory arrangement containing the configuration data bus structure 130 the access control register unit 147 is set to a default value providing no access to the register units 143-146. Thus, it is assured that after a cold start or a reset of the memory arrangement, an access to the hidden register units 143-146 is denied.
The access control register unit 147 may comprise a 32-bit word which is set to a predetermined value to grant access to the register units 143-146. If the configuration data bus structure 130 provides for example an 8-bit data bus, the 32-bit value has to be set in four separate write operations as illustrated in
As described above, the embodiments described above with reference to the figures may be each realized in a dedicated chip or any combination of the embodiments described above may be realized within one chip combining the functionality and characteristics of these embodiments. Furthermore, the embodiments described above may not only be used in a memory arrangement, but may also be used in other arrangements containing configuration data (e.g., in I/O devices of data processing systems).
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
