This application claims priority under 35 U.S.C. §119 to an application filed in the Korean Intellectual Property Office on Feb. 2, 2006 and assigned Serial No. 2006-10260, and an application filed in the Korean Intellectual Property Office on Feb. 2, 2007 and assigned Serial No. 2007-10819, the contents of both of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method and apparatus for transmitting/receiving a signal in a communications system, and in particular to a method for transmitting/receiving a signal by an LDPC (Low Density Parity Check) code.
2. Description of the Related Art
The next generation communications system has been developed as a packet service communications system, which is a high capacity transmission system, to transmit burst packet data to a plurality of mobile stations. As the channel code effectively used for the next generation communications system, the LDPC code, along with the turbo code, has been positively considered for its good performance gain in high speed data transmission and improved reliability attained through effective correction of noise-related errors. Examples of the next generation communications system are the IEEE (Institute of Electrical and Electronic Engineers) 802.16e and 802.11n communications systems.
Referring to
Referring to
As described above, the LDPC code has advantages, as in the turbo code, that the performance gain is superior at high speed data transmission and the reliability of the data transmission is improved by effective correction of the noise-related errors. The cycle of the LDPC code on the factor graph means the loop consisting of the edge connecting the variable node and the check node on the factor graph of the LDPC code, and the size of the cycle is defined as the number of edges. Accordingly, the size of the cycle increases with the number of the edges connecting the variable node and the check node. Thus, the performance of the LDPC code is improved as the cycle size of the LDPC code is increased on the factor graph.
Conversely, as the number of small-sized cycles of the LDPC is increased on the factor graph, the LDPC code suffers performance degradation due to error floor phenomena, impairing the error correction capability. Hence, if there are many small-sized cycles of the LDPC code on the factor graph, the information starting from an arbitrary node belonging to a small-sized cycle returns to itself after a small number of repetition, and thus, the increase of the repetition number results in the increase of the information returns, so that the information update is hindered so as to impair the error correction capability.
Moreover, the LDPC code is more complicated in encoding than the turbo code, making it difficult to encode in real time. In order to reduce the encoding complexity of the LDPC code, a repeated accumulation (RA) has been proposed, but the RA code also suffers limitations in reducing the encoding complexity of the LDPC code.
Therefore, when transmitting/receiving signals using LDPC code in a communications system, a solution is demanded to reduce the encoding complexity of the LDPC code together with enhanced error correction capability.
Accordingly, an aspect of the present invention is to provide a method and apparatus for transmitting/receiving signals by using a zigzag LDPC code in a communications system.
Another aspect of the present invention is to provide a method and apparatus for transmitting/receiving signals by using a zigzag LDPC code in a communications system, which reduces the encoding complexity.
Another aspect of the present invention is to provide a method and apparatus for transmitting/receiving signals by using a zigzag LDPC code in a communications system, which enhances the error correction capability.
According to one aspect of the present invention, a method for transmitting a signal in a signal transmission apparatus of a communications system includes receiving an information vector and encoding the information vector according to a zigzag B-LDPC encoding procedure to generate a zigzag B-LDPC codeword, thereby reducing the encoding complexity together with enhanced error correction capability.
The above and other aspects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawing in which:
Preferred embodiments of the present invention will be described herein below with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.
The present invention provides a method and apparatus for transmitting/receiving signals by means of the zigzag B-LDPC (Block Low Density Parity Check) code in a communications system. This method provides reduction of the encoding complexity together with enhanced error correction. Moreover, the method of transmitting/receiving signals by means of the zigzag B-LDPC code of the invention may be applied to the signal transmission/receiving apparatus of a conventional communications system.
The zigzag B-LDPC code is achieved by designing a Concatenated ZigZag (CZZ) using a structured interleaver so as to enable the CZZ code parity check matrix to have a structured LDPC matrix. Hence, the zigzag B-LDPC code represents the CZZ code having a parity check matrix in the form of the structured LDPC code matrix.
Referring to
The structured zigzag code has a parity check matrix consisting of a partial matrix of a permutation matrix. The permutation matrix is a square matrix with a size of Ns×Ns, of which each row has a weight of 1, and each column also a weight of 1. In this case, the term ‘weight’ represents the number of elements having a non-zero value, and for convenience, it is assumed the non-zero value equals 1. Here, the zigzag B-LDPC code matrix consisting of two layers #1 and #2, respectively, representing a first and a second structured zigzag code. Thus, the zigzag B-LDPC matrix consists of two layers formed by their respective structured zigzag codes.
More specifically, the parity check matrix of the zigzag B-LDPC code consists of a plurality of blocks representing respective matrixes. Hereinafter, the matrix corresponding to each block is called “block matrix,” which is a square matrix with a size of Ns×Ns, as described above. Hence, the block size is Ns. In addition, the parity check matrix of the B-LDPC code consists of an information part corresponding to the information bits contained in the information vector (s) and a parity part corresponding to parity bits. The parity part includes two sub-parity parts belong to their respective structured zigzag codes. Namely, the structured zigzag code also includes an information part and a parity part, which is the sub-parity part.
Furthermore, in
First, each of the block columns constituting the information part of the parity check matrix of the zigzag B-LDPC code has a weight of 1. The fact that each block column has a weight of 1 means that the permutation matrix is attached to only one of the blocks constituting each block column, and 0 (zero) matrix to the other blocks. For example, in
Second, the block matrix at a particular position of the first and the second sub-parity part of the parity check matrix of the zigzag B-LDP code, (e.g., the block matrix corresponding to the one at the uppermost and rightmost position of the plural blocks contained in the first sub-parity part of the first layer and the block matrix corresponding to the one at the uppermost and rightmost position of the plural blocks contained in the second sub-parity part of the second layer) is set as the Z matrix as expressed by the following mathematical Formula 1:
The Z matrix as shown by Formula 1 is obtained by shifting the identity matrix toward the left by one column so as to make all elements of the rightmost column have a value of zero. Thus, if the Z matrix is attached to the block matrix corresponding to the one at the uppermost and rightmost position of the plural blocks contained in the first sub-parity part of the first layer and the block matrix corresponding to the one at the uppermost and rightmost position of the plural blocks contained in the second sub-parity part of the second layer, the number of the block columns produced with a weight of 1 is prevented from becoming Ns. The reason for preventing the number of the block columns with a weight of 1 from becoming Ns is that as the number of columns with a weight of 1 increases in the parity check matrix of the LDPC code, the LDPC performance characteristics are considerably degraded.
Third, the parity part of the parity check matrix of the zigzag B-LDPC code has a weight of non-zero only both in the first sub-parity part of the first layer and in the second sub-parity part of the second layer, and the other sub-parity parts have a weight of zero. Namely, as shown in
Fourth, each of the block matrixes, L111, L122, L133, . . . , L1MM constituting a diagonal of the first sub-parity part of the first layer among the parity part of the parity check matrix of the zigzag B-LDPC code is a permutation matrix, and each of the block matrixes, L121, L132, L143, . . . , L1MM-1 constituting just below parallel to the diagonal is an identity matrix. Hereinafter, the diagonal and the portion below parallel to the diagonal are referred to as ‘dual diagonal’. The other matrices except for the block matrices in the dual diagonal and Z at the uppermost and rightmost position of the first sub-parity part of the first layer are 0 matrixes. Further, the dual diagonal of the second sub-parity part of the second layer, L211, L222, L233, . . . , L2MM and L221, L232, L243, . . . , L2MM-1 are identity matrixes, and the other matrices except for the block matrices in the dual diagonal and Z at the uppermost and rightmost position of the second sub-parity part of the second layer are 0 matrices.
The characteristics of the parity check matrix of the zigzag B-LDPC may be applied to L concatenated structured zigzag codes as follows:
First, each of the block columns constituting the information part of the parity check matrix of the zigzag B-LDPC code has a weight of 1.
Second, the Z matrix is attached to a particular position of the first, the second, . . . , and the L'th sub-parity part of the parity check matrix of the zigzag B-LDPC code, e.g., the block matrix corresponding to the one at the uppermost and rightmost position of the blocks in the first sub-parity part of the first layer, the block matrix corresponding to the one at the uppermost and rightmost position of the blocks in the second sub-parity part of the second layer, . . . , the block matrix corresponding to the one at the uppermost and rightmost position of the blocks in the L'th sub-parity part of the L'th layer.
Third, the parity part of the parity check matrix of the zigzag B-LDPC code has a weight of non-zero only both in the first sub-parity part of the first layer and in the second sub-parity part of the second layer, . . . , and in the L'th sub-parity part of the L'th layer, and the other sub-parity parts have a weight of zero.
Fourth, the dual diagonal of the first sub-parity part of the first layer of the parity check code matrix of the zigzag B-LDPC is constituted as the identity matrixes, the other matrices except for the block matrices in dual diagonal and Z at the uppermost and rightmost position of the first sub-parity part of the first layer are 0 matrices. The dual diagonal of the second sub-parity part of the second layer is constituted as the identity matrixes, the other matrices except for the block matrices in the dual diagonal and Z at the uppermost and rightmost position of the second sub-parity part of the second layer are 0 matrices, and the dual diagonal of the Lth sub-parity part of the Lth layer is constituted as the identity matrices, the other matrices except for the block matrices in dual diagonal and Z at the uppermost and rightmost position of the Lth sub-parity part of the Lth layer are 0 matrices.
In
In
In
As shown in
In operation, the information vector s to be transmitted by the signal transmission apparatus is applied to the assembler 611 and the first to L'th interleavers 613-1 to 613-L. The first to L'th interleavers 613-1 to 613-L interleave the information vector s according to their respectively prescribed interleaving procedures, delivered respectively to the first to L'th encoders 615-1 to 615-L, which usually consist of the accumulators to generate structured zigzag codes. Specifically, the first to L'th encoders 615-1 to 615-L perform an operation similar to the operation performed by accumulator used for generating repeated accumulation (RA) code, continuously accumulating the inputted values to generate the parity bits. Assuming the number of the information bits connected to a single parity bit of the structured zigzag code to be k, the first to L'th encoders 615-1 to 615-L encoders accumulate k information bits to generate one bit as the parity bit delivered to the puncturing device 617. Further, the first to L'th encoders 615-1 to 615-L generate a single parity bit consisting of the accumulated k information bits, delivered to the puncturing device 617. Hence, this is the same operation as generating the convolutional code with a punctured memory value of 1, and the generation is achieved by the following Formula 2:
Formula 2 represents a conventional accumulator outputting the convolutional codes, which are punctured to generate k bits as a unit.
The puncturing device 617 punctures the structured zigzag codes outputted at the coding rate used for the signal transmission apparatus from the first to L'th encoders 615-1 to 615-L, according to a prescribed puncturing pattern, to generate the parity vector delivered to the assembler 611. The operation of the puncturing device 617 has no direct connection with the invention, and is omitted from detailed description. The assembler 611 assembles the information vector (s) and the parity vector p to generate the zigzag B-LDPC codeword.
In
In
In operation, the demodulated vector (x) and the output signal of the deinterleaver 821 are applied to the first decoder 811. Here, the output signal of the deinterleaver 821 is the updated information in the previous decoding. When there is no updated information in the initial decoding, the demodulated vector (x) is only applied to the first decoder 811.
The first decoder 811 decodes the demodulated vector (x) and the output signal of the de-interleaver 821, according to a prescribed decoding procedure, to generate the decoded signal delivered to the first subtracter 813. In this case, the decoding procedure corresponds with the encoding procedure used in the first encoder 715-1 of
The controller 817 retrieves the interleaving and deinterleaving patterns from the memory 815, respectively delivered to the interleaver 819 and the deinterleaver 821 to perform interleaving and deinterleaving according to the patterns. The interleaving and deinterleaving patterns are generated corresponding with the parity check matrix of the zigzag B-LDPC code.
The interleaver 819 interleaves the output signal of the subtracter 813 according to the interleaving pattern to generate the interleaved signal to the second decoder 825 and the second subtracter 823. The second decoder 825 decodes the output signal of the interleaver 819 according to the prescribed decoding procedure to deliver the decoded signal to the switch 827. Here, the decoding procedure corresponds with the encoding procedure used in the second encoder 715-2 of
After completing a predetermined repetition of the decoding operation, the switch 827 is turned on to deliver the output signal of the second decoder 825 to the hard decision unit 829. In this case, the switch may be turned on when completing either a predetermined repetition of the decoding operation or every single decoding operation. When the switch is turned on at every single decoding operation, the parity check may be performed to be used as the reference for ending the repeated decoding operation. Thus, the invention advantageously provides a method of transmitting and receiving signals in a communications system, which employs the zigzag B-LDPC code that the parity check matrix is the CZZ code having the same form as the structured LDPC code, thereby considerably reducing the encoding complexity together with enhanced error correction capability.
While the invention has been shown and described with reference to a certain preferred embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
Number | Date | Country | Kind |
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10-2006-0010260 | Feb 2006 | KR | national |
10-2007-0010819 | Feb 2007 | KR | national |
Number | Name | Date | Kind |
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6895547 | Eleftheriou et al. | May 2005 | B2 |
20060190801 | Shin et al. | Aug 2006 | A1 |
Number | Date | Country |
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102005011959 | Dec 2005 | KR |
1020060093627 | Aug 2006 | KR |
Number | Date | Country | |
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20070220397 A1 | Sep 2007 | US |