BRIEF DESCRIPTION OF THE DRAWINGS
The features of the invention believed to be novel and the elements characteristic of the invention are set forth with particularity in the appended claims. The figures are for illustration purposes only and are not drawn to scale. The invention itself, however, both as to organization and method of operation, may best be understood by reference to the detailed description which follows taken in conjunction with the accompanying drawings in which:
FIG. 1 depicts a two-dimensional model of the present invention simulating wire parasitic capacitance and resistance.
FIG. 2 depicts the two-dimensional model of FIG. 1 with parasitic capacitance models shown.
FIG. 3 depicts a limiting case of a semi-isolated wire for analyzing parasitic wire resistance and capacitance.
FIG. 4 depicts a fully isolated wire model having center interconnect line capacitively coupled to two perpendicular interconnect lines.
FIG. 5 depicts a wire parasitic model for interconnect lines over a perpendicular signal line with no nearby upper level wires.
FIG. 6 depicts the coupling scenario where there are no nearby upper level wires or same level wires.
FIG. 7 depicts a five-level configuration (three-dimensional model) where parasitic couplings from an interconnect line to other interconnect lines at one level above and two levels above as well as to other interconnect lines at one level below and two levels below under study may be represented.
FIG. 8 depicts the parasitic capacitance coupling from an FET gate to nearby contact CA, where contact CA is electrically connected to M1 above it and to diffusion layer RX below it.
FIG. 9 depicts a flow chart of the extraction, simulation, and analysis flow of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
In describing the preferred embodiment of the present invention, reference will be made herein to FIGS. 1-9 of the drawings in which like numerals refer to like features of the invention.
FIG. 1 depicts a two-dimensional model 10 of the present invention simulating wire parasitic capacitance and resistance. Two current carrying, parallel metal signal or interconnect lines M1 and M3 are shown a distance hA and hB, respectively, from three interconnect lines M2, which are perpendicular to the direction and layout of M1 and M3 (shown in the figure as going through the page). The interconnect lines have a known width w and height or thickness t, and are placed a distance s1 from the (first) neighboring wire on the left, and a distance sr from the (first) neighboring wire on the right. The resistance of M2 is at a minimum when the width w and thickness t are maximized. Under this condition, the line-to-line coupling capacitance, CM2-M2 (including both Cleft, and Cright), the capacitance from the M2 wire at the center to M1 lines below, CM2-M1 (also referred to as Cdown), and the capacitance from the M2 wire at the center to the M3 lines above, CM2-M3 (also referred to as Cup), are larger. The largest value of total capacitance Ctotal will occur when the width w and thickness t are maximized and hA, hB are minimized. The largest line-to-line coupling capacitance CM2-M2 will occur when the width w, thickness t, and distances hA and hB are maximized. The parasitic coupling to each metal line of a distributed RC network is depicted from the center metal line under study, and capacitively represented by Cup, Cdown, Cleft, and Cright, as depicted in FIG. 2. The total parasitic capacitance is the summation of each modeled parasitic capacitor: Ctotal=Cup+Cdown+Cleft+Cright=CM2-M3+CM2-M1+2*CM2-M1. Two separate process corners are required for analysis. Inter-level capacitances CM2-M1 and CM2-M3 are maximized when the width, w, and the thickness, t, are maximized, while heights hA, hB are minimized; but line-to-line coupling capacitance CM2-M2 is not at a maximum under the same conditions. Similarly, when the governing parameters w, t, hA, and hB are all maximized, line-to-line coupling capacitance CM2-M2 is at its maximum, but inter-level capacitances CM2-M1 and CM2-M3 are not.
The present invention forms parasitic resistor elements for each wire, where each resistor element is a model call, or a set of library functions, with distribution values for a given modeling program. It also adds parasitic wire capacitor elements where each capacitor element is a model call with its own distributions. By allowing the parasitic values to be represented by modeled algorithmic functions, instead of discrete values, it is possible to predict the detrimental affects that each interconnect line will have on its adjacent neighbors under various configuration scenarios, including frequency dependent conditions.
FIG. 3 depicts a limiting case of a semi-isolated wire for analyzing parasitic wire resistance and capacitance that cannot be easily attained by the prior art method. In a semi-isolated wire condition, M1 and M3 are shown parallel to one another with two M2 interconnect lines running perpendicular therewith. The interconnect line under study, the center M2 line, is given a resistance value R based on the dimensions of the line, and modeled with parasitic capacitance to the adjacent M1, M2, and M3 lines, with capacitors Cdown, Cleft, and Cup, respectively. In this instance, the total capacitance from the center interconnect line, Ctotal, is the sum of the individual parasitic capacitances, such that: Ctotal=Cleft+Cup+Cdown.
Generally, models require a skewing parameter for each predicted value of parasitic coupling, which usually entails maximum, minimum, and nominal values. The present invention involves modeling the wire parasitics as call-up model functions, which allows for continuous analytical skewing results. For example, the capability of adding wire capacitor elements to the analysis as a model call with distributions allows for continuous skewing of separate couplings for the inter-level M2-M1 and M2-M3 capacitors and the line-to-line M2-M2 capacitor.
FIG. 4 depicts a fully isolated wire model having center interconnect line capacitively coupled to two perpendicular interconnect lines M1, M3. The center interconnect line is modeled with a resistor element R based on the line dimensions, and individual parasitic capacitance Cdown and Cup to M1 and M3, respectively. Each capacitor and resistor value is associated with a model call-up function within the analysis tool. The total parasitic capacitance affecting the signal propagation of the center interconnect line is represented by the sum of the individual parasitic capacitance values: Ctotal=Cup+Cdown.
The parasitic model call-up feature of the present invention may also be employed when no nearby upper level wires are configured. FIG. 5 depicts a wire parasitic model for interconnect lines M2 over a perpendicular signal line M1 with no nearby upper level wires. The center interconnect line under study is modeled with a resistor element R, and given the model call-up parasitic capacitances functions Cleft, Cright, and Cdown, which capacitively connect the center line to adjacent signal lines. The total parasitic capacitance affecting the signal propagation and time delay of the center interconnect line is represented by the sum of the individual parasitics: Ctotal=Cleft+Cright+Cdown.
FIG. 6 depicts the simplest coupling scenario, where there are no nearby upper level wires or same level wires. Interconnect line M1 is shown with resistance R, and capacitively coupled directly to the substrate 60. In this configuration, a single model call-up is sufficient to represent the parasitic affects on the signal performance of M1. The total parasitic capacitance is shown as the single capacitor model, Cdown, between M1 and the substrate, such that Ctotal=Cdown.
FIG. 7 depicts a five-level configuration (3D model) where parasitic couplings from interconnect line M2 connects to interconnect line M3, one level above, and M4, two levels above, and from M2 to interconnect line M1, one level below, and the substrate, two levels below. As depicted in FIG. 7, the total parasitic capacitance Ctotal is the sum of the individual parasitic capacitor model call-ups surrounding the interconnect line under study: Ctotal=Cleft+Cright+Cup+Cdown+Ctop+Cbottom. The parasitic modeling call-up feature allows the user to handle multiple sub-layer designs. Moreover, in the modeling prediction of a device, the parasitic modeling functions allow one to account for the calculation of coupling influences on signal performance.
FIG. 8 depicts the parasitic capacitance coupling 84 from a FET poly (PC) gate 80 to contact CA. Contact CA is electrically connected to M1 above it and to diffusion layer RX below it. Here, the parasitic capacitance 84 from the PC gate to the CA+M1 portion of the device may be modeled under various scenarios for determining the operation of the FET, and the detrimental affects that the parasitics will have on the FET's signal.
In a general analytical tool such as SPICE, and the like, the three-level (2D wire model) and five-level (3D wire model) parasitic coupling models of the present invention may be coded as a set of functions which may be linked with the tool's simulator. This allows for the wire parasitic models to be heavily used in schematic simulations and analysis of critical nets. The present invention may also be used as a stand-alone tool for parameterizing the timing of circuits or devices.
Moreover, the present invention may be employed as part of a base algorithm for an extraction tool. In this manner, an extraction tool algorithm utilizing the present invention would generally include the following steps: a) reading the layout files; b) performing device recognition; c) calling active devices models; d) calling passive device models; e) calling parasitic coupling models; f) treating the parasitic coupling models as device model calls to obtain process variations in Monte Carlo analysis, skewing, and tracking with other device model behavior. The parasitic models will have continuous prediction features, where the variations of the parasitic couplings may be used in Monte Carlo simulations and worst case circuit performance calculations
Additionally, the present invention may be effectively used during ring-oscillator simulations where the effects of parasitic resistance and capacitance can no longer be ignored. Variations in parasitic couplings are needed for best case/worst case simulation scenarios and Monte Carlo statistical simulations.
The extraction, simulation, and analysis flow of the present invention may be represented by the flow chart of FIG. 9. A circuit layout 90 is inputted to the extraction tool 92. The extraction tool may be Synopsys' StarRcxt, Mentor Graphics'CalibrXrc, Cadence Assura's RCX, Diva, Sequence's Columbus RF Star-Rcxt, CalibrXrc, IBM's Efficient Rapid Integrated Extraction (ERIE), or the like. A semiconductor technology file 94, which includes BEOL level scheme, level names, and the like, is fed into the extraction tool 92. A SPICE netlist 96 is created. The netlist will include FET model calls, passive device model calls, and parasitic resistance, capacitance, and inductance model calls. The netlist is then input into a SPICE simulator 98, such as HSPICE, Spectre, UltraSim, IBM PowerSpice, and the like. Also inputs to the SPICE simulator 98 include model process files 100 for FET models, passive device models 102, and parasitic skewing parameters 104. Unique to the present invention, the model process files 100 are used to generate the parasitic interconnect R, L, C model functions 106, which are also input to the SPICE simulator 98. The output of the SPICE simulator 98 results in an analytical assessment of the circuit's electrical/electronic performance results 108. Correlation among the parasitic couplings above, below, right, and left of an interconnect line is captured. Correlation among the RF FETs, passive devices, and parasitic couplings (R, L, and C) are also captured.
Implementing the present invention in an extraction tool would include the following steps: a) read the layout files; b) perform device recognition; c) call FET models and passive device models, wherein the models contain process distributions and their effects on model behavior; d) modeling each parasitic wire resistor element as a model call-up with associated distributions, with each distribution being able to continuously vary from its own 3σ minimum (best case or worst case) value to its nominal value and then to its 3σ maximum (worst case or best case) values; e) adding parasitic capacitive and/or inductive wire elements as model call-ups with associated distributions; f) enabling Monte Carlo analysis and/or skewing on the element models; and g) performing circuit analysis of the selected models.
While the present invention has been particularly described, in conjunction with a specific preferred embodiment, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore contemplated that the appended claims will embrace any such alternatives, modifications and variations as falling within the true scope and spirit of the present invention.
Patent Application
20080028353
