Method for Utilizing a Memory Interface to Control Partitioning of a Memory Module

Abstract

Described herein are at least one apparatus and methods for implementing partitioning in memory cards and modules. A representative memory card/module in accordance with the invention may include a memory device(s), and a memory interface which includes a data bus, a command line and a clock line. The memory card/module may further include a memory controller coupled to the memory device(s) and to the memory interface. The memory card/module may include means for controlling the partitioning of the memory device(s). The memory controller may be configured to operate the memory device(s) in accordance with the partition information.

Description

FIELD OF THE INVENTION

The present invention relates to the technical field of memory cards or modules. It also relates to memory cards or modules using flash and/or ROM technology. More specifically the invention relates to a simple way to implement partitioning in memory cards and modules such as e.g. MultiMediaCard (MMC) cards, SD memory cards or Memory Sticks where a conventional memory cards or modules having only single partition.

The present invention relates to memory cards or modules known for example as MMC cards or e.g. SD cards or Memory Sticks. The MMC and SD specification describes a memory card functionality in a certain card form factor and with a certain electric interface and a data exchange protocol for the exchange of data. This invention describes some additional functionality needed to make system more usable and reliable as embedded mass memory.

BACKGROUND OF THE INVENTION

The properties of MMC cards are disclosed e.g. in the MMC specification available at the web page “http://www.mmca.org/compliance/buy_speclMMCA_System SummaryV41.pdf’.

Presently, the memory card specification does not describe partitioning or other details about the internal functionalities of memory cards. Therefore, the functionality of internal firmware in case of wear leveling, garbage collection, data compaction, bad block management and other memory technology related issues, which are required for proper card functionality, are card specific and cannot be controlled by host.

The flash memory layout of modem mobile terminals has usually multiple partitions. These partitions are usually binary partitions (read-only) and read-write partitions such as known from hard discs. The read-only partitions may be updated only a few times in device lifetime and the probability of their corruption must be very low. The read-write partitions are more heavily used but also there data consistency is very important. There may also be some read-write partitions that contain data needed for device operation (has to be stored highly secured way).

In existing memory cards/modules and memory card specification partitions are not defined (i.e. all data in card described or viewed as being located in a same partition). This means higher risk of data corruption for example during sudden power-cut-off (power supply interruption) situations (if at the same time erase or write operation internally in card going on) and results in lower data security.

Even though data security of data stored m currently used storage card is not yet a highly relevant topic it should be considered as always desirable to increase the data security of storage media.

SUMMARY OF THE INVENTION

According to one aspect of the present invention a memory card or module is provided. The memory card or module comprises at least one memory device, a memory interface, and a memory controller. The memory interface comprises at least a data bus, a command line and clock line. In the memory card or module, the memory controller is connected to the (at least one) memory device and to the memory interface. The memory card or module according to the invention is further provided with means for controlling the partitioning of the (at least one) memory device. Additionally, the memory controller is configured to operate the (at least one) memory device in accordance with the partitioning.

The present invention discloses an abstraction layer (with configurable/controllable partitions) on top of existing memory card or module specifications. The partitions, what can be applied to guarantee low probability of data corruption. In practice, this means an additional set of commands (functionalities), states or parameters have to be supported by the memory cards/modules compared to conventional mass memories.

The term “memory module” is used to denote memory cards and memory modules, not to obscure the specification with terms like “memory cards/modules”. Additionally the term “at least one” is omitted in connection with the memory device, as it should be clear that all occurrences of memory devices might also be embodied as multiple memory devices. The expression memory module is synonymously used with the expression “memory card or module” and is used to denote memory cards, embedded memory devices and devices with a memory module interface (such as e.g. a MMC- or SD-card interface) comprising a memory device.

In one example embodiment of the present invention the memory interface is a MMC/SD-card interface. In this example embodiment, the memory module is implemented as a MultiMediaCard (MMC) with the standardized interface and form factor. In another example embodiment, the memory module implemented as a Secure Digital (SD) card with the standardized interface and form factor. In another example embodiment, the memory module is implemented as a chip scale package with the standardized interface and form factor. This implementation allows the use of partitionable memory module in mobile (cellular) telephones, in portable cameras, media (e.g. MP3) playback devices and the like.

In another example embodiment of the present invention, the partitioning information comprises information selected from but not limited to the group of: size of each partition, start address/stop address of each partition, read only access/read-write access, wear leveling information, number of spare blocks, and fixed partition or reconfigurable partition.

The present invention discloses an abstraction layer (with configurable/controllable partitions) on top of existing memory module specifications. The partitions may be applied to guarantee low probability of data corruption. In practice, it means an additional set of commands (functionality); states or parameters have to be supported by the memory modules compared to conventional mass memories. With this set of commands, it should be possible to define several partitions on the memory device of the memory module. It may also be possible to restrict the maximum amount of partitions that for example to 16 (32, 64, or even 1024). By default whole card may be configured (be visible) as a single read/write partition with default features. The size of each partition (including e.g. a start address and a stop address or a start address and a partition size) may be adjusted or selected separately for each partition.

It is also envisaged to define for each partition, if the partition allows, read only access or read-write access.

It is also contemplated to define wear-leveling information separately for each partition. Wear leveling information may for example comprise if the wear leveling is activated or deactivated for each partition, and may be also comprise information about which memory (cells or) blocks are actually worn off and which memory (cells or) blocks are used to replace them. It is contemplated to allow only blocks inside the particular partition to be used for the wear leveling of that partition. This kind of “partition internal” wear leveling could minimize data interference between different partitions and simplify recovering after sudden power off.

It is contemplated and envisaged to define for each partition the number of spare block to be reserved for wear leveling operations per partition. It is to be noted that in case of partitions with expectably very different write access rates different numbers of spare blocks may be assigned for each partition. The amount of spare blocks (required if e.g. run time block errors occur) per each partition may be configurable by the host system. Spare blocks of particular partitions may be located in the same address range what is specified for partition. Spare blocks of a particular partition may be located in a common pool of spare blocks. As the probability of block-errors in read-only partitions might not have any spare blocks at all.

It is also contemplated to define for each partition the number of spare blocks to be reserved for at least one fixed partition or at least one reconfigurable partition.

It is also envisaged to create the read-only partitions first as continuous space (area of the memory device) and to create read-write partitions after that. This approach simplifies the access to additional spare blocks in case that wear leveling capacities of a partition are not sufficient and need to be extended (partition shifting).

It is possible to implement the memory device, the memory controller and the means for controlling the partitioning of the memory device on a single integrated chip. It is also envisaged to implement this embodiment only by integrating the memory controller and the means for controlling the partitioning and only a part of the memory device on a single chip e.g. in this case the memory module of a memory card comprises a number of memory chips, connected to the memory interface. It is also contemplated to use a number of memory units (located e.g. on a single or a number of chips) forming together the memory device.

In an example embodiment the memory device is a flash memory.

In still another example embodiment of the present invention a the memory controller is configured to check the correctness of the partition information. It may be checked if the selected partition fits to memory module geometry. It may also be checked if partitions are overlapping. It may also be determined if a minimal amount of spare blocks may be provided for a memory partition to allow wear leveling. It is also contemplated to monitor the partition information and additionally evaluate and reallocate the partitions (e.g. for expanding spare blocks, moving partitions and the like). With these abilities, the memory module is able to accommodate even larger “blackouts” of memory cells/sections/areas. Subsequently to a respective check, a negative result of the checking operation may be output (a positive result of the check may also be provided to a user but will not be considered as providing any useful information). Thereby, a user may be informed that a repartitioning operation is considered necessary.

According to another aspect of the present invention, a method for utilizing a memory interface of a memory module is provided. The memory interface comprises (at least) a data bus, a command line and a clock line. The method comprises receiving at a memory controller of a memory module, a single indicative of partitioning information, storing the partitioning information in a memory module, and operating the memory device by the memory controller in accordance with the partition information. Throughout the specification the term “signal” should be understood in broad sense, i.e., should cover both sending software through interface and hardware signaling. It may be noted that the memory interface is the interface of the memory module to a host device.

In an example embodiment of the method of the present invention, the signal indicative of partitioning information comprises information selected from but not limited to the group of: size of each partition, start address/stop address of each partition, read only access/read-write access, wear leveling information for each partition, number of spare blocks for each partition and if a partition is a fixed partition or reconfigurable partition. After storing the partitioning information the method may further comprise extracting the information from the received signal and defining partitions of a memory device. The operating the memory device in accordance with the partition information may also comprise accessing the memory device in accordance with the defined partitions, and controlling read/write access and wear leveling for each partition separately.

In yet another example embodiment of the method of the present invention the memory controller is configured to check the correctness of the partition information. Thereby it can be checked if the selected partition fits the memory module/device geometry. It may also be checked it the partition information defines, e.g. overlapping partitions. It may be determined if a minimal amount of spare blocks are provided for a memory partition to enable wear leveling. Subsequently to a respective check, a negative result of the operation may be output. Thereby, a user can be informed that a repartitioning operation is considered as being necessary.

According to another aspect of the present invention, a method for utilizing a memory interface of a memory module is provided. The memory interface comprises a data bus, a command line and a clock line. The method comprises sending from a host device, a signal indicative of partitioning information, at a memory controller of a memory module and, operating the memory device by the memory controller in accordance with the partition information.

In an example embodiment of the method of the present invention, the signal indicative of partitioning information comprises information selected from but not limited to the group of: size of each partition, start address/stop address of each partition, read only access/read-write access, wear leveling information for each partition, number of spare blocks for each partition, and if a partition is a fixed partition or reconfigurable partition. After storing the partitioning information the method may further comprise extracting the information from the received signal and defining partitions of a memory device. Operating the memory device in accordance with the partition information may also comprise accessing the memory device in accordance with the defined partitions, and controlling read/write access and wear leveling for each partition separately.

According to yet another aspect of the invention, a software tool is provided comprising program code means for carrying out the method of the preceding description of utilizing a memory interface when the program product is run on memory module. According to this and the following aspects of the present invention, the memory interface include at least a data bus, a command line and a clock line.

According to another aspect of the present invention, a computer program product downloadable from a server for carrying out the method of the preceding description of utilizing a memory interface is provided when the program product is run on memory module.

According to yet another aspect of the invention, a computer program product is provided comprising program code means stored on a computer readable medium for carrying out the methods of the preceding description of utilizing a memory interface when the program product is run on memory module.

According to another aspect of the present invention, a computer data signal is provided. The computer data signal is embodied in a carrier wave and represents a program that makes the computer or the memory module (it is received at or forwarded to) perform the steps of the method contained in the preceding description of utilizing a memory interface is provided when the program product is run on memory module.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts an example of typical memory layout (showing partition boundaries).

FIG. 2 depicts a visualization of allowed (inter-partition) and not allowed (extra-partition) wear-leveling operations.

FIG. 3 is a schematic view of a memory card according to one aspect of the present invention.

FIG. 4 is a flowchart depicting an implementation of the method of the present invention.

FIG. 5 is a flowchart depicting another implementation of the method of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

In the detailed description that follows, identical components have been given the same reference numerals, regardless of whether they are shown in different embodiments of the present invention. In order to clearly and concisely illustrate the present invention, the drawings may not necessarily be to scale and certain features may be shown in somewhat schematic form.

FIG. 1 depicts an example of typical embedded mass memory layout. The mass memory comprises different partitions delimited by the boldly sketched partition boundaries. In each partition, a part is depicted as “visible partition” to a host (depicted as the blank areas).

Additionally to the partitions visible to a host invisible spare areas are provided (invisibly to a host) in each partition. On each memory module, an area is reserved memory module internally (as an area in the memory core/module or as an extra means for controlling the partitioning of the memory device) for storing data for bad-block management and memory module metadata.

FIG. 2 depicts an example of allowed (in-partition) wear leveling and not allowed (interpartition) wear-leveling operations. In contrast to known memory modules without partitioning, inter-partition wear leveling may not occur (due to a lack of partitions especially of different partitions). In figure it is indicated that it is allowed to shift (or wear level) different block within a single partition (within the partition boundaries indicted by the bold lines1 as indicated by the arrows. However, it is not allowed to use inter-partition wear leveling as indicated by the interrupted arrow crossing a partition boundary. Anyhow, the present invention allows to shift the partitions, which in turn may allow to shift partitions first and subsequently perform an inpartition wear leveling process that otherwise would have been an inter-partition wear leveling process.

FIG. 3 is a schematic view of a memory card according to one aspect of the present invention. An MMC card (Multi-Media Card) is depicted with the usual electrical interface (comprising contacts to a data bus, for power supply, ground level, command and clock signal) and having to' the usual MMC form factor. As in a conventional MMC-card, the contacts are connected to a memory interface controller serving to control the data exchange via the external contacts of the MMC card. The memory interface controller is connected via the memory controller to the memory device. In contrast to conventional MMC-cards, the memory controller is connected to a dedicated units/means for controlling the partitioning of the memory device to simplify the figure the means for controlling the partitioning of the memory device is named partitioning means in the figure. In this means for controlling the partitioning of the memory device the memory controller can store partition information related to the memory device, to define in the memory device partition areas indicated by the interrupted dotted lines in the memory device (memory area or memory core). It may be noted that the means for controlling the partitioning of the memory device may also be embodied as a dedicated area (or even partition area) of the memory device itself, to enable the MMC-card provide partitionability with only a single memory device. (It may be envisaged to hardcode the memory area (address) allocated to the means for controlling the partitioning of the memory device in the memory controller itself.)

With a memory device to store partition information (and, if the processing capability of the memory controller is sufficient) the memory module is enabled to operate the memory device or the access to the memory device in accordance with partition data of the means for controlling the partitioning of the memory device.

For the sake of clarity, additional components o the MMC card such as the memory device interface controller (which may also be comprised of the memory controller) or memory device power detection (to reset the memory device interface and the memory interface controller) have been omitted.

FIG. 4 is a flowchart depicting an implementation of the method of the present invention. The flowchart starts with the step of receiving at a memory controller of a memory card, a signal indicative of partitioning information. This information may be received from an external host via the memory interface at a memory (module) interface controller. Then the received partitioning information is provided to means for controlling the partitioning of the memory device assigned to the memory controller. Then the memory controller of the memory module operates the memory device in accordance with the partition information stored of the means for controlling the partitioning of the memory device.

Even though not explicitly cited in the flowchart, the partitioning information may be selected from but not limited to the group of: size of each partition, start address/stop address of each partition, access type of the partition such as read-only-access or read-write-access, wear leveling information for each partition (which blocks are worn and which blocks replace them), and number of spare blocks for each partition (which may freely be selected in dependence of an MTBF (mean time before failure) to be achieved). After receiving the partitioning information the method may further comprise extracting the information from the received signal, storing the extracted information and defining partitions (with respective partition parameters) on the a memory device. Operating the memory device in accordance with the partition information may also comprise (defining the partitions, with all partition parameters) accessing the memory device in accordance with the defined partitions (i.e. partition wise), and controlling read/write access and wear leveling for each partition separately.

FIG. 5 is a flowchart depicting another implementation of the method of the present invention. The flowchart starts with the step of sending from a host device to a memory controller of a memory module, a signal indicative of partitioning information. Then the host device operates the memory device in accordance with the partition information. This implementation represents the host device side of the present invention.

This may be implemented by a special set of commands that could be defined for control partitioning. For example, the EXT_CSD command (specified in MMCA v4.1 specification) may be used as basis. It should be possible to define amount of partitions and separately for each partition: a start address, an end address, if the partition allows read only or read-write operations, if wear leveling is activated or not. It may be envisaged to (by default) not allow wear leveling in read-only partitions.

With the present invention, it becomes possible to do re-partition the storage of the memory module freely at any time (if it is connected to a host). The description of dedicated access procedures, wear leveling procedures and partitioning information data formats have been omitted for not obscuring the description of the figures.

By using partitioning in memory cards/modules, it may be possible to reduce risk of data corruption. With partitioning it is also possible to keep read-only data in fresh non-wear leveled areas (data retention is also depends from erase count). This has the additional advantage that spare regions (areas or blocks) may additionally be used in the read/write regions (areas or blocks) improving the expected overall lifetime of a memory module. By dividing the memory (core) to several partitions may reduce the lifecycle of certain read-write areas (each memory block has limited erase count), but in view of the benefit from higher data consistency this seem to be acceptable.

It is to be noted that the present invention is able to control the internal lower level partitioning of memory cards/modules from a host device (via a memory module interface such as the MMC/SD card interface). Up to now, existing cards did not offer this possibility but use a fixed internal physical partitioning of memory device (and then provide a FAT partitioning on top of that). In contrast to the known approaches, the present invention adds a third partitioning layer between the card internal physical layer partition and the FAT partition.

Partition in document means: Memory module is plurality of sectors visible to user. The plurality of sectors (continuous address space) is divided on sections with some module specific granularity. One section is a partition. Each partition has a set of features (RO, R/W, etc). Set of features are describing the behavior of the partition to the user/host.

This application contains the description of implementations and embodiments of the present invention with the help of examples. It will be appreciated by a person skilled in the art that the present invention is not restricted to details of the embodiments presented above, and that the invention can be implemented in another form without deviating from the characteristics of the invention. The embodiments presented above should be considered illustrative, but not restricting. Thus, the possibilities of implementing and using the invention are only restricted by the enclosed claims. Consequently, various options of implementing the invention a determined by the claims, including equivalent implementations, also belong to the scope of the invention.

Claims

1. (canceled)

2. A memory module comprising: at least one memory device;a memory interface;a memory controller coupled to the at least one memory device and to the memory interface, the memory controller configured to perform acts comprising: receiving partition information associated with the at least one memory device;based at least in part on the partition information, logically partitioning the at least one memory device to enable one or more partitions of the at least one memory device; andoperating the at least one memory device in accordance with the partition information, the partition information comprising size information indicating a size of the one or more partitions and protection information indicating whether at least one of the one or more partitions is write protected.

3. The memory module according to claim 2, wherein the partition information is included in a single command.

4. The memory module according to claim 2, wherein the memory interface comprises a MultiMediaCard or Secure Digital (MMC/SD) card interface.

5. The memory module according to claim 2, wherein the partitioning information further comprises at least one of: a start address and a stop address of each partition,wear-leveling information associated with each partition,a number of spare blocks associated with each partition, oran indicator identifying whether each partition is a fixed partition or a reconfigurable partition.

6. The memory module according to claim 2, wherein the at least one memory device comprises a flash memory.

7. The memory module according to claim 2, wherein the at least one memory device and the memory controller are implemented on a single chip.

8. The memory module according to claim 2, wherein the memory controller is configured to check a correctness of the partition information.

9. A method comprising: receiving, by a memory controller that is coupled to at least one memory device and to a memory interface, partition information associated with the at least one memory device;based at least in part on the partition information, logically partitioning the at least one memory device to enable one or more partitions of the at least one memory device; andoperating the at least one memory device in accordance with the partition information, the partition information comprising size information indicating a size of the one or more partitions and protection information indicating whether at least one of the one or more partitions is write protected.

10. The method according to claim 9, wherein the partition information is included in a single command.

11. The method according to claim 9, wherein the memory interface comprises a MultiMediaCard or Secure Digital (MMC/SD) card interface.

12. The method according to claim 9, wherein the partitioning information further comprises at least one of: a start address and a stop address of each partition,wear-leveling information associated with each partition,a number of spare blocks associated with each partition, oran indicator identifying whether each partition is a fixed partition or a reconfigurable partition.

13. The method according to claim 9, wherein the at least one memory device comprises a flash memory.

14. The method according to claim 9, wherein the at least one memory device and the memory controller are implemented on a single chip.

15. The method according to claim 9, wherein the memory controller is configured to check a correctness of the partition information.

16. A host device comprising: at least one memory device;a memory interface;a memory controller coupled to the at least one memory device and to the memory interface, the memory controller configured to perform acts comprising: receiving partition information associated with the at least one memory device;based at least in part on the partition information, logically partitioning the at least one memory device to enable one or more partitions of the at least one memory device; andoperating the at least one memory device in accordance with the partition information, the partition information comprising size information indicating a size of the one or more partitions and protection information indicating whether at least one of the one or more partitions is write protected.

17. The host device according to claim 16, wherein the partition information is included in a single command.

18. The host device according to claim 16, wherein the memory interface comprises a MultiMediaCard or Secure Digital (MMC/SD) card interface.

19. The host device according to claim 16, wherein the partitioning information further comprises at least one of: a start address and a stop address of each partition,wear-leveling information associated with each partition,a number of spare blocks associated with each partition, oran indicator identifying whether each partition is a fixed partition or a reconfigurable partition.

20. The host device according to claim 16, wherein the at least one memory device comprises a flash memory.

21. The host device according to claim 16, wherein the at least one memory device and the memory controller are implemented on a single chip.

22. The host device according to claim 16, wherein the memory controller is configured to check a correctness of the partition information.