BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates an illustrative graph including a number of nodes.
FIG. 2 illustrates schematically an embodiment of the Minimum Value Accelerator in accordance with an embodiment of the present invention.
FIG. 3 shows a schematic view of one implementation of a lookup circuit used in the Minimum Value Accelerator.
FIG. 4 illustrates a lookup operation of the Minimum Value Accelerator with retrieval of the next vertex from Active Queue Array.
FIG. 5 schematically illustrates a Candidate Queue Array and associated data structures.
FIG. 6 is a flow chart of the general process of determining the shortest path between a single source vertex and multiple vertices that may be implemented in accordance with an embodiment of the present invention.
FIGS. 7A, 7B, and 7C are detailed flow charts of the process shown in FIG. 6.
FIG. 8 is a detailed flow chart of part of the process shown in FIG. 7C.
FIG. 9 illustrates a computer that may be used to implement the present invention.