Patent Application
20080084737
These and other objects and advantages of the present invention will become more fully apparent from the following detailed description when read in conjunction with the accompanying drawings with like reference numerals indicating corresponding parts throughout, wherein:
A new and novel method for correcting over-erased memory cells in an array of flash EPROM memory cells fabricated on a semiconductor integrated circuit substrate so as to achieve zero column leakage is described. In the following description, numerous specific details are set forth, such as specific circuit configurations, components, and the like in order to provide a thorough understanding of the present invention. However, it should be apparent to those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known processes, circuits and control lines, not particularly relevant to the understanding of the operating principles of the present invention, have been purposely omitted for the sake of clarity.
Referring now in detail to the drawings, there is shown in
It will be recalled from
The flash EPROM memory array 110 is formed of a plurality of memory cells MC11 through MCnm arranged in an n×m matrix on a single semiconductor substrate by known CMOS integrated circuit technology. It should be noted that the structural circuit components and their interconnection of the memory array 110 of
In particular, the memory cells MC11 through MC1m are arranged in the same row and have their selection terminals connected to the common word line WL. Similarly, the cells MC21 through MC2m are arranged in the same row and have their selection terminals connected to the common word line WL1. This is likewise done for each of the remaining rows in the array 110. Thus, the memory cells MCn1 through MCnm are arranged on the same row and have their selection terminals connected to the common word line WLn. Furthermore, the memory cells MC11 through MCn1 are arranged in the same column and have their data terminals connected to the common bit line BL0. Similarly, the cells MC12 through MCn2 are arranged in the same column and have their data terminals connected to the common bit lines BL1. This is likewise done for each of the remaining columns in the array 110. Thus, the memory cells MC1m through MCnm are arranged in the same column and have their data terminals connected to the common bit line BLm.
Each of the memory cells MC11 through MCnm is comprised of one of the corresponding floating gate array transistors QP11 through QPnm. The array transistors QP11 through QPnm function as a memory transistor for storing data “1” or “0” therein. Each of the array transistors QP11-QPnm has its gate connected to one of the rows of word lines WL-WLn, its drain connected to one of the columns of bit lines BL-BLm, and its source connected to an array ground potential VSS.
The improved over-erase correction process or method for achieving zero column leakage of the present invention for use in the memory array 110 of
In
In decision block 614, the conventional OEC method steps are caused to continue in the block 612 via line 607 until all of the columns have a leakage current less than or equal to about 2-4 uA. When this is reached, the process goes to block 616 via line 609 where the program-over-erase correction (POEC) method steps of the present invention are performed so as to further reduce the residue column leakage current to a zero value. In decision block 618, the POEC method steps are caused to continue in the block 616 via line 611 until the leakage current in each of the columns is equal to zero uA. When this occurs, the process is completed and proceeds to block 620 via line 613. The present over-erase correction method can be then repeated via line 615.
With particular reference again to the memory array of
In decision block 706, a sense amplifier SA1 functioning as a comparator receives a reference current IREF on its one input and receives a bit line current IBL on its other input. The result on the output of the SA1 indicates whether the selected bit line or column has passed or failed. If there is a failure indicative of an over-erased bit, the process goes to OEC block 708 via line 701 where a voltage pulse having a magnitude of approximately +3.0-+5.0 volts and a width of about 100 uS is applied to the selected bit line BL0 with the column leakage. Then, the process will go back to the OECV block 704 via line 703 where the over-erase-correction verify mode of operation will be repeated. This is continued until the column leakage current is reduced to about 2-4 uA. When this occurs, the process goes to decision block 710 to determine if all of the columns have been OEC verified. If not, then in the block 712 the address is increased by 1 and the next column in sequence (BL1, BL2, and so on) is OEC verified by the block 704 via line 705. When all of the columns have been OEC verified, the process goes to the block 616 of
With particular reference again to the memory array of
In decision block 806, a sense amplifier SA1 functioning as a comparator receives a reference current IREF on its one input and receives a core cell current ICOR on its other input. The result on the output of the SA1 indicates whether the selected core cell has passed or failed. If there is a failure indicative of an over-erased bit, the process goes to POEC block 808 via line 801 where a positive bias voltage having a magnitude of about +2.0 volts is applied to each word line in a third timed sequence on a word line by word line basis and where simultaneously a voltage pulse having a magnitude of approximately +3.0-+5.0 volts and a width of about 10 uS is applied to each bit line in a fourth timed sequence on a bit line by bit line basis. Then, the process will go back to the POECV block 804 via line 803 where the over-erase-correction verify mode of operation will be repeated. This is continued until the leakage current is reduced to zero uA. When this occurs, the process goes to decision block 810 to determine if all of the core cells in all of the word lines have been POEC verified. If not, then in the block 812 the address is increased by 1 and the next word line in sequence (WL1, WL2, and so on) is POEC verified by the block 804 via line 805. When the core cells in all of the word lines have been POEC verified, the process goes to the block 620 of
It should be clear to those skilled in the art that the present over-erase correction method utilizes in general a two-stage approach. The first stage of the novel present method is to use the conventional OEC method steps to correct the column leakage current to a relatively small, non-zero value. The second stage of the new method is to use the POEC method steps to further correct the residue column leakage current to zero. It will be noted that if only the first stage is used, the column leakage current will not be corrected to zero within a reasonable amount of time. This is because the correction speed slows down when the threshold VT is increased close to 0 volts since the electron injection efficiency onto the floating gate will decrease exponentially with (VG−VT). Further, since a threshold VT close to zero corresponds to a very small current (e.g., less than 1 uA) under the conventional OEC verify mode of operation in which VG=0V, it will be difficult to reliably sense due to the small signal-to-noise ratio.
On the other hand, if only the second stage is used a selected memory core cell that does not need correction can be falsely corrected due to a leaky cell in the same column. This is because when the selected memory cell (good cell) is POEC verified the current from the leaky cell will be added to the current of the selected memory cell so as to increase the total current to a level indicative of a bad cell (one that needs correction). However, after the leaky cell is corrected later on so that the column leakage current is removed, the selected memory cell that was corrected initially will have a VT which will be too high. Thus, the selected memory cell was falsely corrected. In order to avoid this kind of false correction, the conventional OEC method must be applied first so as to reduce the column leakage current to about 2-4 uA. Thereafter, the POEC method is applied so as to further reduced the column leakage current to zero uA.
From the foregoing detailed description, it can thus be seen that the present invention provides a method of correcting over-erased memory cells in a flash EPROM memory device after erase so as to achieve zero column leakage. The correction method of the present invention is achieved by applying first positive pulse voltages to each bit line on a bit line by bit line basis until the column leakage current in each bit line is reduced to a relatively small value. Thereafter, a positive bias voltage is applied to each word line in a first timed sequence on a word line by word line basis. Second positive pulse voltages are simultaneously applied to each bit line in a second timed sequence on a bit line by bit line basis when the positive bias voltage is being applied to a first word line until the column leakage current in the corresponding bit line is reduced to zero and is then repeated for each subsequent remaining word line.
While there has been illustrated and described what is at present considered to be a preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the true scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the central scope thereof. Therefore, it is intended that this invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out the invention, but that the invention will include all embodiments falling within the scope of the appended claims.
