"MTL Storage Cell", S. K. Wiedmann, IBM Tech. Dis. Bul., vol. 21, No. 1, Jun. 1978, pp. 231, 232. |
"Merged-Transistor Logic (MTL)-A Low Cost Bipolar Logic Concept", Berger et al., IEEE Jour. of Solid-State Circuits, vol. SC-7, No. 5, Oct. 1972, pp. 340-346. |
"Integrated Injection Logic: A New Approach to LSI", by Hart et al., IEEE Journal of Solid-State Circuits, vol. SC-7, No. 5, Oct. 1972, pp. 346-351. |
IBM TDB "Restore Circuitry for Bit/Sense System", by S. K. Wiedmann, vol. 13, No. 6, Nov. 1970, pp. 1705-1706. |
IEEE Journal of Solid-State Circuits, vol. SC-13, No. 5, "A Fast 7.5 ns Access 1K-Bit RAM for Cache-Memory Systems", by K. Kawarada et al., pp. 656-663. |
IEEE Journal of Solid-State Circuits, vol. SC-2, No. 4, Dec. 1967, "Beam-Lead Sealed-Junction Semiconductor Memory with Minimal Cell Complexity", by J. E. Iwersen et al., pp. 196-201. |
IEEE Journal of Solid-State Circuits, vol. SC-6, No. 5, Oct. 1971, "Bipolar Dynamic Memory Cell", by H. H. Henn, pp. 297-300. |
Electronics, May 2, 1974, "Current Steering Simplifies and Shrinks 1k Bipolar RAM", by J. E. Gersbach, pp. 110-114. |
Electronics, vol. 47, No. 5, Mar. 7, 1974, "Pinch Load Resistors Shrink Bipolar Memory Cells", by S. K. Wiedmann, pp. 130-133. |