Patent Application
20250218338
The present invention relates to a method of controlling a display panel, and more particularly, to a method of controlling a display panel in a hybrid mode.
In a display system, the application processor (AP) transmits display data to the display driver circuit through a mobile industry processor interface (MIPI). There are two commonly used transmission modes on the MIPI: the command mode and the video mode. In order to gain the benefits of both the command mode and the video mode, the industry has proposed a hybrid mode for the MIPI specification, which is equivalent to a mixture of the command mode and the video mode.
In the prior art, the display driver circuit supporting the hybrid mode is requested to perform mode switching according to the usage scenario of the display system, which may be determined by the AP. In detail, the AP should first determine the usage scenario and then send a command to inform the display driver circuit to change its operation mode. The AP may not determine the most appropriate image sending method in every usage scenario; hence, the power saving effect achieved by the hybrid mode is limited.
It is therefore an objective of the present invention to provide a method of controlling a display panel and a related display driver circuit supporting the hybrid mode, in order to solve the abovementioned problems.
An embodiment of the present invention discloses a method of controlling a display panel for a display driver circuit, wherein the display driver circuit has a frame buffer. The method comprises steps of: receiving a first frame of display data and sending the first frame of display data to the display panel by bypassing the frame buffer; starting counting time in a time period for receiving the first frame of display data, to determine whether a timeout occurs; receiving a second frame of display data after the timeout occurs; and writing the second frame of display data into the frame buffer.
Another embodiment of the present invention discloses a display driver circuit for controlling a display panel, wherein the display driver circuit has a frame buffer. The display driver circuit receives a first frame of display data and sends the first frame of display data to the display panel by bypassing the frame buffer; starts counting time in a time period for receiving the first frame of display data, to determine whether a timeout occurs; receives a second frame of display data after the timeout occurs; and writes the second frame of display data into the frame buffer.
Another embodiment of the present invention discloses a method of controlling a display panel for a display driver circuit, wherein the display driver circuit has a frame buffer. The method comprises steps of: receiving a first frame of display data and writing the first frame of display data into the frame buffer; receiving a second frame of display data which is not in response to a control signal of the display driver circuit after receiving the first frame of display data; outputting the second frame of display data to the display panel by bypassing the frame buffer.
Another embodiment of the present invention discloses a display driver circuit for controlling a display panel, wherein the display driver circuit has a frame buffer. The display driver circuit receives a first frame of display data and writes the first frame of display data into the frame buffer; receives a second frame of display data which is not in response to a control signal of the display driver circuit after receiving the first frame of display data; and outputs the second frame of display data to the display panel by bypassing the frame buffer.
Another embodiment of the present invention discloses a method of controlling a display panel for a display driver circuit, wherein the display driver circuit has a frame buffer. The method comprises steps of: receiving a plurality of display data; determining a frequency of the plurality of display data; and writing the plurality of display data into the frame buffer or outputting the plurality of display data to the display panel by bypassing the frame buffer according to the frequency.
Another embodiment of the present invention discloses a display driver circuit for controlling a display panel, wherein the display driver circuit has a frame buffer. The display driver circuit receives a plurality of display data; determines a frequency of the plurality of display data; and writes the plurality of display data into the frame buffer or outputs the plurality of display data to the display panel by bypassing the frame buffer according to the frequency.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
According to the specification of the mobile industry processor interface (MIPI), the display driver circuit supporting the command mode contains a frame buffer. When the display driver circuit is operated in the command mode, the display data from the MIPI may be written into the frame buffer and then read out from the frame buffer at appropriate time point(s) to refresh the panel. The video mode is applied to a display driver circuit that may not contain a frame buffer. When receiving display data through the MIPI, the display driver circuit may directly forward the display data to refresh the display panel. In the hybrid mode, the host processor may send images in a manner similar as in the video mode, but the display driver circuit may selectively write the received display data into the frame buffer or control the display data to bypass the frame buffer to be directly output to the display panel for refresh.
A low temperature polycrystalline oxide (LTPO) panel supports an extremely low frame rate such as 1 Hz. If the display panel is directly switched to the extremely low frame rate of 1 Hz from the display of a high frame rate of 120 Hz, it will easily cause visual effect problems such as screen flickering. Therefore, the MIPI Association has proposed an adaptive refresh panel (ARP) mechanism to enter the extremely low frame rate from the high frame rate display in panel refresh through the sequential frequency down-conversion method, so as to solve the above visual effect problems and also obtain power saving effects. Based on the ARP operations, the host processor will not actively send images when the images are not updated, and will send images when receiving a control signal sent by the display driver circuit. At this time, the display driver circuit may send the control signal to instruct the host processor to send images at specific time points during the ARP operations, to achieve the purpose of sequential frequency down-conversion.
In general, the host processor in the hybrid mode sends images in a similar manner as in the video mode, but the display driver circuit may selectively write the display data into the frame buffer or control the display data to bypass the frame buffer to be directly forwarded to the display panel. Therefore, as for the ARP operations, the display driver circuit only needs to receive the updated display data once from the host processor and store these display data in the frame buffer, and then reads out the display data by controlling the frame buffer using the internal clock, to perform panel refresh with sequentially down-converted frequencies. The display driver circuit does not need to trigger the host processor to send images multiple times, and this significantly reduces the power consumption of image sending on the MIPI and improves the display efficiency.
The display driver circuit 104 may process the display data and convert the display data into data voltages to be output to the pixels on the display panel 106. In an embodiment, the display driver circuit 104 may be implemented in an integrated circuit (IC) to realize a display driver IC (DDIC). In the following descriptions, the display driver circuit will be abbreviated as DDIC, and those skilled in the art would know that the DDIC described hereinafter may represent a display driver circuit capable of driving a display panel and implemented in any manner.
Since the DDIC 104 supports the hybrid mode, the DDIC 104 may include a memory 112, in which a frame buffer is implemented. Examples of the memory 112 may include a random access memory (RAM), but not limited thereto.
The display panel 106 may be any type of display device, which may be, but not limited to, an organic light emitting diode (OLED) panel, liquid crystal display (LCD) panel, or any other panel performing display by receiving scan control.
In various embodiments of the present invention, the DDIC 104 supports the hybrid mode, where the display data received by the DDIC 104 may be selectively written into the frame buffer implemented in the memory 112, or forwarded to the display panel 106 to perform refresh by bypassing the frame buffer. The operations of writing the display data into the frame buffer mean that the received display data may be compressed in an appropriate manner and then the compressed display data are stored in the memory 112. The operations of forwarding the display data to the display panel 106 mean that a processing circuit of the DDIC 104 may process the display data and convert the display data into corresponding data voltages, and an output driver of the DDIC 104 may output the data voltages to the display panel 106. In such a situation, neither the display data nor the data voltages are stored in the memory 112.
In detail, the DDIC 204 may decide to be operated in the read/write mode or bypass mode according to the still indication SI. In the read/write mode, the DDIC 204 may write the received display data into the frame buffer (which may be implemented in a built-in memory such as the memory 112 shown in
As can be seen from above, the AP 202 may determine the value of the still indication SI by using the logic unit in its upper layer, where the upper layer may determine the operation mode before the graphics layer performs image processing and generates the output display data. For example, the algorithm of the AP 202 may determine an application (app) that the mobile phone needs to enter belongs to which type, determine the image content attributes that the app may display, and then instruct the AP 202 which mode to enter (e.g., the still mode or dynamic mode). The AP 202 may also correspondingly send the still indication SI to the DDIC 204, to instruct the DDIC 204 to enter the read/write mode or bypass mode. When this app is operating, the AP 202 and the DDIC 204 are configured to always operate in the predetermined mode and cannot be switched dynamically.
However, an app does not necessarily have all dynamic images or all still images, but only one of the operation modes may be selected for this app, resulting in limited benefits of the hybrid mode. In addition, the manufacturer of the mobile phone may not be able to correctly understand the attributes of each app and select the accurate operation mode. For example, the AP 202 may be predefined to operate in the still mode when it is not able to determine the app's attribute. However, if this app has more dynamic images but the DDIC 204 is instructed to be operated in the read/write mode, the DDIC 204 will perform a large number of read and write operations, resulting in considerable power consumption.
First, the AP 202 is in the still mode and may be displaying a still image such as a background image. Correspondingly, the DDIC 204 is operated in the read/write mode, and its frame buffer is enabled to store the previously received display data. At this time, the AP 202 does not need to send display data with the vertical synchronization signal VS to the DDIC 204, and the DDIC 204 may read the frame buffer through an internal clock, to output the display data to the display panel to perform refresh. Note that the horizontal synchronization signal HS may be a signal utilized by the DDIC 204 to synchronize various display operations, and this signal may be received from the AP 202 through the MIPI or a general purpose output (GPO) interface, or may be generated internally in the DDIC 204.
In an embodiment, in the read/write mode, the DDIC 204 may gradually decrease the refresh rate through the sequential frequency down-conversion method, e.g., gradually adjusting from 120 Hz to 1 Hz, in order to meet the requirements of visual effects under the ARP operations. Therefore, the display data for refresh may be read out from the frame buffer with sequentially down-converted frequencies.
After the user opens an app to trigger the AP 202 to enter the dynamic mode, the AP 202 may start to continuously send the vertical synchronization signal VS and display data to the DDIC 204. At the same time, the AP 202 may send a command CMD containing the still indication SI to the DDIC 204, to instruct the DDIC 204 to enter the bypass mode. The command CMD may be sent through the vertical front porch (VFP) in the display data channel of MIPI, but not limited thereto. In the bypass mode, the DDIC 204 may control the received display data to bypass the frame buffer to be directly sent to the display panel. The DDIC 204 may continuously receive display data from the AP 202 to refresh the panel, and the read/write functions of the frame buffer are disabled.
In the example of
In the dynamic mode, the AP 202 may continuously transmit high-speed display data such as in the frame rate of 120 Hz, and the DDIC 204 in the bypass mode may forward the display data to the display panel for refresh by bypassing the frame buffer. When receiving a command CMD having the still indication SI that indicates the start of a still image, the DDIC 204 enters the read/write mode. In the read/write mode, the frame buffer of the DDIC 204 keeps enabled. As long as the AP 202 transmits any display data through the MIPI, the DDIC 204 will write the display data into the frame buffer. Since the DDIC 204 performs mode switching only based on the still indication SI from the AP 202, if no relevant command is received and the AP 202 continuously sends images, a large amount of power consumption in the read/write operations of the frame buffer will be generated.
In general, in order to save the storage space, the display data needs to be compressed before being written into the frame buffer, and the operations of reading the display data from the frame buffer requires corresponding decompression. The operations of compression and decompression require a large amount of calculation and thus generate considerable power consumption. For example, as shown in
For example, when receiving the display data with a higher frequency, the DDIC 504 may determine that the AP 502 sends images with a higher frame rate, which means that the image sending frequency may be higher than a first threshold. At this time, the DDIC 504 may enter the bypass mode to directly output the display data to the display panel by bypassing the frame buffer, thereby reducing the number of reads and writes in the frame buffer. The reduced read/write operations will further reduce the power consumption required for the memory. When receiving the display data with a lower frequency, the DDIC 504 may determine that the AP 502 sends images with a lower frame rate, which means that the image sending frequency may be lower than a second threshold (which may be identical to or different from the first threshold). At this time, the DDIC 504 may enter the read/write mode and write the received display data into the frame buffer, and then read out the display data from the frame buffer at appropriate time point(s) to refresh the panel, e.g., through the control of the internal clock. This will reduce the power consumption of image sending through the MIPI.
In an embodiment, the DDIC 504 may use a timer or a timeout counter to determine the image sending frequency of the AP 502. As long as the image sending frequency falls to a certain threshold, a timeout will be triggered, and the DDIC 504 may enter the read/write mode accordingly.
As for the AP 502, it only needs to send images with a variable frame rate based on the display image content; that is, the AP 502 may continuously update the display data with a higher frame rate for dynamic images (e.g., when playing videos), while transmitting no display data or few display data for still images. The logic unit in the upper layer of the AP 502 does not need to determine whether the transmitted images are dynamic images or still images, and the AP 502 does not need to determine which scenario the app to be opened by the user belongs to. Therefore, regardless of the usage scenario, the AP 502 only needs to send images based on the predetermined timing, so there is no dynamic mode or still mode. In addition, the AP 502 does not need to send a command CMD or a still indication SI to notify the DDIC 504 to change the operation mode. The DDIC 504 may be switched between the read/write mode and the bypass mode by itself without being instructed by any command or indication received from the AP 502.
The AP and the DDIC described in the following embodiments may be the AP 502 and the DDIC 504 in the display system 50 shown in
First, assuming that the display system is playing a movie with a high refresh rate, the AP continuously outputs display data in a high frequency through the MIPI at this time. Since the DDIC receives continuous full-speed display data along with the vertical synchronization signal VS sent by the AP, it may operate in the bypass mode, where the frame buffer is disabled and bypassed, and the DDIC continuously refreshes the display panel based on a series of display data received from the AP. More specifically, the read and write functions of the frame buffer included in the DDIC are disabled. In such a situation, the DDIC may control the display data to bypass the frame buffer and directly forward the display data to the display panel for refresh.
After the movie is completely played, the AP will no longer actively update images and stop transmitting display data. The AP may gradually decrease the image sending frequency, e.g., through the sequential frequency down-conversion method. When the image sending frequency falls below a certain level, the DDIC may leave the bypass mode to enter the read/write mode, and the subsequently received display data will be written into the frame buffer.
The DDIC may perform the mode switch through time counting. In an embodiment, the DDIC may start counting time in each time period for receiving a frame of display data. For example, the DDIC may start counting time every time it receives a vertical synchronization signal VS from the AP, where the vertical synchronization signal VS indicates the start of a time period for transmitting a frame of display data. The DDIC may also set a timeout length, so as to determine whether a timeout occurs based on the timing result. When determining that the timeout occurs, which means that no vertical synchronization signal VS is received for a predetermined period of time exceeding the timeout length, the DDIC may leave the bypass mode to enter the read/write mode. The timeout means that the AP does not actively update images for more than a period of time, which means that the frequency of the AP sending images falls below a certain level. For example, the DDIC may set the timeout length to an appropriate value so that it is expected to enter the read/write mode when the frequency of the output vertical synchronization signal VS falls below 20 Hz, which means that the image sending frequency of the AP falls below 20 Hz.
Through the above timeout mechanism, the DDIC does not need to receive any command from the AP to indicate whether to enter the read/write mode. The DDIC may leave the bypass mode and enter the read/write mode only based on the frame rate or frequency of the received display data.
The above time counting scheme used for determining the occurrence of timeout may be implemented in any manner. In an embodiment, a timeout counter may be applied to calculate the number of horizontal synchronization signals HS continuously received after the DDIC receives the vertical synchronization signal VS, so as to determine whether the timeout occurs. Therefore, when the number of accumulated horizontal synchronization signals HS exceeds a specific value, the DDIC may determine that a timeout occurs and thereby enter the read/write mode.
After entering the read/write mode, the DDIC may refresh the display panel by reading out the display data from the frame buffer. As shown in
Subsequently, when the AP needs to update the display images while the DDIC is in the read/write mode, the AP will start to continuously transmit the updated display data. When receiving the updated display data continuously transmitted by the AP, the DDIC may automatically return to the bypass mode. Similarly, the DDIC performs determination entirely based on the way the AP sends images, and thus does not need to receive an additional command CMD or still indication SI from the AP to indicate whether to enter the bypass mode.
Step 902: Receive a first frame of display data IMGB1 and refresh the display panel with the display data IMGB1 by bypassing the frame buffer.
Step 904: Start counting time in a time period for receiving the display data IMGB1, to determine whether a timeout occurs.
Step 906: Output a control signal TE2 to instruct the AP to transmit a second frame of display data IMGB2 to the DDIC when determining that the timeout occurs.
Step 908: Receive the vertical synchronization signal VS in response to the control signal TE2.
Step 910: Leave the bypass mode to enter the read/write mode.
Step 912: Receive the display data IMGB2 in the frame period defined by the vertical synchronization signal VS, and write the display data IMGB2 into the frame buffer.
Referring to the waveforms of
In response to the control signal TE2, the AP may send a vertical synchronization signal VS with the display data (e.g., IMGB2) to the DDIC. Since the DDIC enters the read/write mode, it will write the display data IMGB2 into the frame buffer. In general, the display data IMGB2 output based on the trigger of the control signal TE2 are not actively updated images, and thus the image content of the display data IMGB2 may be identical to the image content of the display data IMGB1 (e.g., both are IMGB, as shown in
Note that the AP supports a variable frame rate, where the frequency that the AP transmits a series of frames of display data is variable. The variable frame rate may be realized in any manner. For example, the AP may reduce the image sending frequency by extending the VFP interval, and different VFP lengths may correspond to different frame rates. As shown in
According to the MIPI specification, the DDIC and the AP are requested to communicate with each other through a control signal TE1. The DDIC may send the control signal TE1 to the AP, to indicate whether the AP is allowed to write images at this time. In this embodiment, the control signal TE1 may be realized by using a control pin connected between the AP and the DDIC. The control pin in the high level indicates a state that image writing is allowable, and in the low level indicates a state that image writing is not allowable. For example, when reading out (decompressing) display data from the frame buffer for refreshing the display panel, the DDIC will pull the control signal TEL low to inform the AP that it cannot write images at this time. In addition, when the DDIC receives the vertical synchronization signal VS and starts to receive and process display data from the AP, it will also pull the control signal TEL low until the display data is completely received. Therefore, as for the switching in the hybrid mode, the DDIC may use an additional control signal TE2 to communicate with the AP, to instruct the AP to send images at an appropriate time point. In an embodiment, the control signal TE2 may be a control pin connected between the AP and the DDIC, such as a GPO pin. In an embodiment, the control pin may be in the low level in usual, and the DDIC may pull the control pin to the high level to generate a signal pulse when it needs to send the control signal TE2.
The purpose of sending the control signal TE2 to instruct the AP to send images is that, in the bypass mode, the DDIC may directly forward the display data to the display panel to perform refresh without updating the data stored in the frame buffer. Therefore, when the DDIC enters the read/write mode from the bypass mode, those stored in the frame buffer may be older display data. At this time, the DDIC should preferably trigger the AP to transmit the latest display data to update the frame buffer, thereby ensuring that the subsequent display data read out from the frame buffer are correct. As mentioned above, since the AP has stopped updating the image content, it will still transmit the same display data in response to the control signal TE2.
Note that the implementation of using the GPO pin to forward the control signal TE2 is merely an exemplary embodiment of the present invention. In fact, the DDIC may send the control signal TE2 to the AP in any manner. In other embodiments, the control signal TE2 may be sent through any interface connected between the AP and the DDIC, such as the inter-integrated circuit (I2C) interface, serial peripheral interface (SPI), or MIPI, but not limited thereto.
Step 1202: Receive a first frame of display data IMGB and write the display data IMGB into the frame buffer.
Step 1204: Receive the vertical synchronization signal VS which is not in response to a control signal of the DDIC.
Step 1206: Leave the read/write mode to enter the bypass mode.
Step 1208: Receive a second frame of display data IMGC in the frame period defined by the vertical synchronization signal VS, and refresh the display panel with the display data IMGC by bypassing the frame buffer.
Referring to the waveforms of
Subsequently, the DDIC receives a vertical synchronization signal VS from the AP and the received vertical synchronization signal VS is not in response to a control signal TE2 of the DDIC, which means that the AP starts to actively send images through the MIPI. At this time, the DDIC may determine that the AP is ready to start image updating, and will be automatically switched to the bypass mode from the read/write mode. The DDIC then receives the display data IMGC in the frame period defined by this vertical synchronization signal VS, and outputs the display data IMGC to the display panel for refresh by bypassing the frame buffer. In fact, after entering the bypass mode, the DDIC will directly forward the received display data to the display panel by bypassing the frame buffer until the DDIC returns to the read/write mode. Note that since the image content is updated, the received display data (e.g., IMGC, IMGD, IMGE . . . ) may be at least partially different or entirely different.
As can be seen, in addition to sending the vertical synchronization signal VS, horizontal synchronization signal HS and display data, the AP does not need to send any other command or still indication to the DDIC. The DDIC only needs to determine whether to be switched to the bypass mode according to the image sending behavior of the AP.
Note that the present invention aims at providing a timing control mechanism that allows the DDIC to be switched between the read/write mode and the bypass mode when the display system is operated in the MIPI hybrid mode. Those skilled in the art may make modifications and alterations accordingly. For example, the timing in
As shown in
In the frame period corresponding to the display data IMGC, the DDIC does not receive the vertical synchronization signal VS of the next image frame before the timeout occurs; hence, the DDIC determines that the AP transmits display data with a slower frequency (i.e., its image sending frequency may be lower than a specific threshold). Therefore, when receiving the next display data IMGD after timeout, the DDIC may stay in the read/write mode and write the display data IMGD into the frame buffer. Subsequently, in the frame period corresponding to the display data IMGD, the DDIC receives the vertical synchronization signal VS of the next frame of display data IMGE before the occurrence of timeout, i.e., the counted time has not reached the timeout length TLB. Therefore, the DDIC may determine that the display data IMGE are received with a frequency greater than a specific threshold, and thus determine that the AP is ready to start a high-speed image sending. In such a situation, the DDIC may be switched to the bypass mode.
In another embodiment, after the DDIC in the bypass mode enters the read/write mode due to the trigger of a timeout, the DDIC will not output the control signal TE2 to instruct the AP to send images. Instead, the DDIC may wait until the AP needs to update the image content and actively transmits new display data to the DDIC, and then write the new display data into the frame buffer. After the new display data are received, the DDIC may update the frame buffer by using the new display data, and start the subsequent panel refresh operations by reading out the display data from the frame buffer.
For example, as shown in
In this embodiment, when leaving the bypass mode, the DDIC enters the MIPI command mode to read and write display data, to perform the read/write operations on the display data based on the MIPI specification. The command mode serves to replace the read/write mode of the previous embodiments. When the DDIC enters the command mode, the AP may also send a memory writing packet (not illustrated) to control the DDIC to start the operation of writing the frame buffer. In the command mode, the AP will not send the vertical synchronization signal VS and the horizontal synchronization signal HS through the MIPI, and thus the internal horizontal synchronization signal HS is instead utilized by the DDIC.
The abovementioned operations of data transmission and panel refresh based on the operation mode may be summarized into a control process 160, as shown in
Step 1602: Receive a plurality of display data.
Step 1604: Determine a frequency of the plurality of display data.
Step 1606: Write the plurality of display data into the frame buffer or output the plurality of display data to the display panel by bypassing the frame buffer according to the frequency.
The detailed operations and alterations of the control process 160 are illustrated in the above descriptions, and will not be narrated herein.
In the present invention, the DDIC switches the operation mode according to the behavior of the AP transmitting display data, rather than being instructed by a command sent by the AP, so that the power saving benefits may be optimized. In general, many apps may display still images in most situations, but there are several scenarios where the images need to be updated frequently. If the conventional method of determining whether each app should operate in the still mode or dynamic mode based on the usage scenario is applied, only one of the operation modes can be selected, and the obtained power saving effect may not be satisfactory. A simulation result of long-term operations of mobile phones shows that if the AP determines the usage scenario through the upper layer and uses a still indication to notify the DDIC to switch modes, the saved power consumption is limited. In contrast, through the method of the present invention, the DDIC may apply the bypass mode when the AP sends images in a high speed and apply the read/write mode when the AP stops outputting high-speed display data, where the operation modes may be switched by the DDIC itself according to the image sending behavior of the AP. The power consumption saved is about 10 times that of the conventional method.
To sum up, the present invention provides an operation method applied to the MIPI hybrid mode, to control the DDIC to be switched between the bypass mode and the read/write mode. The DDIC does not receive any command or indication from the AP, but only needs to perform mode switching according to the image sending behavior of the AP. The DDIC in the bypass mode may use a timeout mechanism to determine that the image sending frequency of the AP is lower than a threshold value when the timeout occurs but no vertical synchronization signal is received, and may be switched to the read/write mode accordingly. In an embodiment, the DDIC in the read/write mode may be switched to the bypass mode when receiving images sent by the AP, or switched to the bypass mode when determining that the image sending frequency of the AP is higher than a threshold value through another timeout mechanism. In an embodiment, an additional transmission interface may be joined between the DDIC and the AP, allowing the DDIC to send a control signal when entering the read/write mode, to instruct the AP to send images for updating display data stored in the frame buffer. In another embodiment, the DDIC may not send the control signal when entering the read/write mode; instead, the DDIC waits for the AP updating images and actively outputting the updated display data, then writes the display data into the frame buffer, and performs the subsequent self-refresh operations based on the display data stored in the frame buffer. In an embodiment, the DDIC may also support the command mode, and when the AP stops sending the horizontal synchronization signal, the DDIC may generate an internal horizontal synchronization signal by itself to perform display control. Through the operations of the present invention, the benefits of the command mode and the video mode may be obtained simultaneously in the applications of the hybrid mode, and the obtained power saving effect may be maximized.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
This application claims the benefit of U.S. Provisional Application No. 63/615, 278, filed on Dec. 28, 2023. The content of the application is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63615278 | Dec 2023 | US |
