Patent Application
20060072274
This application claims the benefit of Taiwan application Serial No. 93129941, filed Oct. 1, 2004, the subject matter of which is incorporated herein by reference.
1. Field of the Invention
The invention relates in general to a method of controlling surge current in fan modules and apparatus thereof, and more particularly to a method of controlling surge current in fan modules and apparatus thereof, applied in a blade server.
2. Description of the Related Art
Referring to
However, at the time when the power is inputted to rotate the fan motors 104 and 108, surge currents will be generated. If there is more than one fan motor actuated simultaneously in the blade server 100, all the surge currents generated will accumulate in a certain region of the control circuit. The accumulating surge currents may reach several tenth times or even several hundred times of the surge current generated by a single fan motor. The large current mentioned above will shut down the power supply at a short time or reset all the main boards or function modules in the system or even cause error operations. All these will cause data in the blade server 100 got lost or the lift-time of the interior electronic components shortened or even broken, which is a very serious problem with regard to the blade server 100. Therefore, in order to solve the undue surge current issue, the circuit for controlling the actuation of fan motors is required.
In order to prevent the undue surge current issue, most of the present methods control fan motors to be actuated at different time by using control chips. However, these methods not only increase the cost and the design difficulty, but also enhance the loading of the manage platform in the blade server.
It is therefore an object of the invention to provide a method of controlling surge current in fan modules and apparatus thereof, applied in a blade server. The invention can solve the issue of the undue accumulation of surge currents generated by several fan motors or fan modules actuated simultaneously.
The invention achieves the above-identified object by providing an apparatus for controlling surge current in fan modules applied in a blade server. The blade server includes the fan module. The fan module includes a first fan motor and a second fan motor. The blade server generates a control signal for controlling the first fan motor and the second fan motor. The apparatus includes a first delay device, a first driver, a second delay device, and a second driver. The first delay device is for receiving and delaying the control signal for a period of first time to output a first delay control signal. The first driver receives the first delay control signal for driving the first fan motor. The second delay device is for receiving and delaying the control signal for a period of second time to output a second delay control signal. The second driver receives the second delay control signal for driving the second fan motor. The first time is not equal to the second time, the first fan motor and the second fan motor respectively receive the first delay control signal and the second delay control signal at different time, and a first surge current in the first fan motor and thus a second surge current in the second fan motor are not generated at the same time.
Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
Referring to
The blade server 200 generates and transmits a control signal FAN_ID to the fan module 220. The first delay device 202 receives and delays the control signal FAN_ID for a period of first time t1 to output a first delay control signal DFAN_ID. The first driver 204 receives the first delay control signal DFAN_ID1 for driving the first fan motor 206. Similarly, the second delay device 208 receives and delays the control signal FAN_ID for a period of second time t2 to output the second delay control signal DFAN_ID2. The second driver 210 receives the second delay control signal DFAN_1D2 for driving the second fan motor 212. The first time t1 is not equal to the second time t2. Therefore, the first fan motor 206 and the second fan motor 212 respectively receive the first delay control signal DFAN_ID1 and the second delay control signal DFAN_ID2 at different time, and thus the first surge current in the first fan motor 206 and the second surge current in the second fan motor 212 will not be generated at the same time.
Furthermore, referring to
The second RC. circuit 208 includes a second switch Q2, a third capacitor C3, a fourth capacitor C4 and a second impedance R2. The second switch has a second switch control terminal, a first terminal and a second terminal. For example, the second switch is a N-channel MOSFET Q2, the second switch control terminal is the gate G2 of the transistor Q2, the first terminal of the second switch is the drain D2 of the transistor Q2, and the second terminal of the second switch is the source S2 of the transistor Q2. Since the second RC circuit 208 has same circuit structure and operation principle with the first RC circuit 202 except for the time constant, any detail of the second RC circuit is unnecessarily given here. When the control signal FAN_ID is inputted to the second RC circuit 208, the second switch is turned on and the second delay control signal DFAN_ID2 is generated at the second node N2 after a period of second time t2 according to the parameters R2, C3, and C4.
Moreover, the first driver 204 at least includes a transistor QA and a first power switch 306 while the second driver 210 includes a transistor QB and a second power switch 308. The first delay control signal DFAN_ID1 is for controlling the transistor QA while the second delay control signal DFAN_ID2 is for controlling the transistor QB. When the first delay control signal DFAN_ID1 is inputted to the first driver 204, the transistor QA is turned on and the first power switch 306 electrically coupled to the transistor QA is then switched on, and the first fan motor 206 starts to rotate as receiving the power supplied by the power source VDC. When the second delay control signal DFAN_ID2 is inputted to the second driver 210, the transistor QB is turned on and the second power switch 308 electrically coupled to the transistor QB is then switched on, and the second fan motor 208 starts to rotate as receiving the power supplied by the power source VDC.
As mentioned above, for the first RC circuit 202 has a different RC value from the second RC circuit 208, that is, the value (R1×C1) is unequal to the value (R2×C2), the delay time t1 of the first delay control signal DFAN_ID1 is different from the delay time t2 of the second delay control signal DFAN_ID2, and the power-on time of the transistors QA and QB is also different. Therefore, the actuating time of the first fan motor 206 differs from that of the second fan motor 210 and thus the first surge current in the first fan motor 206 and the second surge current in the second fan motor 212 are not generated at the same time.
Referring to
According to the spirit of the invention, the first module RC circuit 402 and the second module RC circuit 404 have respectively different time constant α, which can give rise to different delay time mt1 and mt2. The first module RC circuit 402 has a third switch, a fifth capacitor C5, a sixth capacitor C6 and a third impedance R3. The third switch Q3 has a third switch control terminal, a first terminal, and a second terminal. For example, the third switch is a N-channel MOSFET Q3, the third switch control terminal is the gate G3 of the transistor Q3, the first terminal of the third switch is the drain D3 of the transistor Q3, and the second terminal of the third switch is the source S3 of the transistor Q3. The gate G3 is for receiving the control signal MFAN_ID while the source S3 is coupled to a constant voltage, such as the ground voltage. The third impedance R3 has one terminal coupled to a voltage source VCC and the other terminal coupled to the third node N3, which is coupled to the drain D3 via the fifth capacitor C5. The sixth capacitor C6 has one terminal coupled to the third node N3 and the other terminal coupled to the ground voltage. The first module RC circuit 402 outputs a first delay control signal MDFAN_ID1 at the third node N3. When the module control signal MFAN_ID is inputted to the first module RC circuit 402, the third switch Q3 is turned on and the first module delay control signal MDFAN_ID1 is generated at the third node N3 after a period of first module time mt2 according to the parameters R3, C5, and C6.
The second module RC circuit 404 has the same circuit structure with the first module RC circuit 402 except for the different values of impedance R and capacitor C. The second module RC circuit 404 includes a fourth switch, a seventh capacitor C7, an eighth capacitor C8 and a fourth impedance R4. The fourth switch is such as a N-channel MOSFET Q4. Since the second module RC circuit 404 has the same circuit structure with the first module RC circuit 402, any detail of the second RC circuit is unnecessarily given here. Similarly, When the module control signal MFAN_ID is inputted to the second module RC circuit 404, the fourth switch Q4 is turned on and the second delay control signal DFAN_ID2 is generated at the fourth node N4 after a period of second time mt2 according to the parameters R4, C7, and C8.
The apparatus of controlling surge current in a fan module disclosed by the embodiment uses simple RC circuits providing different time constants to generate the first surge current in the first fan motor and the second surge current in the second fan motor at different time. The apparatus of controlling surge current in several fan modules according to another embodiment also uses the first and the second module RC circuits providing different time constants to generate the first surge current in the first fan module 410 and the second surge current in the second fan module 420 at different time.
While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
| Number | Date | Country | Kind |
|---|---|---|---|
| 93129941 | Oct 2004 | TW | national |
