Patent Application
20240339066
The present disclosure relates to the field of signal processing, and more particularly, to a method of data transmission for reducing data loss and a display device thereof.
Nowadays, the electronic industry is developing rapidly, and various electronic products such as mobile phones, computers and game consoles have become an indispensable part of people's life. In order to meet the more abundant use requirements, the functions of electronic products are becoming more and more powerful, and their internal circuits are becoming more and more complicated. Therefore, Electro Magnetic Interference (EMI), information transmission performance improvement and other issues have also become the key consideration in electronic product research and development.
Electro Magnetic Interference refers to the influence of the circuit system on the peripheral circuit system through conduction or radiation. EMI will reduce the performance of the circuit, and it may lead to the failure of the entire device in serious cases. With the development of technology, high resolution picture and high picture update rate are inevitable trends of display devices in the future. However, with the improvement of resolution and picture update rate, the amount of data transmission becomes quite huge. In order to adapt to this trend, it is necessary to increase the frequency and energy of signals for data transmission. When the frequency and energy of signals for data transmission are increased, it will produce serious electromagnetic radiation interference effect. Therefore, how to reduce the electromagnetic radiation interference effect of electronic display device and also ensure the high-quality transmission of display picture so as to meet the increasingly abundant display requirements is an urgent problem to be solved at present.
According to an embodiment of the invention, a method of data transmission in a display device includes monitoring a data rate of a pixel packet in an active area of a frame, synchronizing a clock according to the data rate to generate a synchronized clock, and clocking data in the pixel packet using the synchronized clock.
According to another embodiment of the invention, a display device includes a timing controller, a transmission line, and a source driver coupled to the timing controller via the transmission line. The source driver monitors a data rate of a pixel packet in an active area of a frame, synchronizes a clock according to the data rate to generate a synchronized clock, and clocks data in the pixel packet using the synchronized clock.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
In order to make the objectives, technical solutions and advantages of the present application more apparent, the exemplary embodiments according to the present disclosure will be described in detail below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited by the exemplary embodiments described herein.
Furthermore, in the specification and the drawings, steps and elements that are substantially the same or similar are denoted by the same or similar reference signs, and repeated descriptions of these steps and elements will be omitted.
Furthermore, in the specification and the drawings, elements are described in singular or plural forms according to the embodiments. However, the singular and plural forms are appropriately selected for the proposed situations only for convenience of explanation, not intended to limit the present disclosure thereto. Therefore, singular forms may include plural forms, and plural forms may also include singular forms, unless the context clearly indicates otherwise.
Furthermore, in the specification and the drawings, the involved terms “first/second” are only used to distinguish similar objects, and do not represent a specific order of objects. Understandably, “first/second” may be interchanged in a specific order or sequence when allowed, so that the embodiments of the present disclosure described here may be implemented in an order other than those illustrated or described herein.
Furthermore, in the specification and the drawings, the adopted terms such as “upper”, “lower”, “vertical” and “horizontal”, etc. which relate to orientation or positional relationship are used only for describing the embodiments conveniently according to the present disclosure, and are not intended to limit the present disclosure thereto. Therefore, they should not be construed as a limitation to the present disclosure.
Furthermore, in the specification and the drawings, unless otherwise specified, “connection” does not necessarily mean “direct connection” or “direct contact”. Here, “connection” may mean both the function of fixation and electrical communication.
In order to facilitate the description of the present disclosure, the concepts related to the present disclosure are introduced below.
Electro Magnetic Radiation widely exists in the use process of various electronic products. With the increasingly powerful functions and faster operation speed of electronic products, Electro Magnetic Interference has become a key consideration in the design of electronic products. The methods to reduce Electro Magnetic Interference mainly include: reducing the energy of electromagnetic signal transmitting end, Spread Spectrum clocking (SSC) and so on. Among them, the Spread Spectrum clocking makes the frequency of high-speed clock jitter continuously in a certain range along with time, such that the energy of electromagnetic radiation in the frequency domain is evenly distributed in a certain bandwidth frequency range, thus a peak value and an average value of electromagnetic radiation energy decrease accordingly.
At present, for a display device based on a point-to-point transmission architecture, the spread spectrum of display signal (that is, the data signal) between T-CON and SD is all taking Unit Interval (UI) as the basic unit of frequency jitter (that is, the frequency of the display signal changes in each UI, regardless of the active time and the blanking time). Although it could effectively reduce Electro Magnetic Interference, it will also increase the total jitter (TJ), which increases the difficulty of processing the display signal of the display device.
Specifically, for the spread spectrum method with UI as the basic unit for frequency jitter, the data rate for signal transmission will be constantly changed with UI as the basic unit in the whole signal transmission process. Therefore, although this method could avoid the accumulation of electromagnetic radiation energy at a fixed frequency, such that the electromagnetic radiation energy in the frequency domain is evenly distributed in a certain bandwidth frequency range, thus reducing a peak value and an average value of electromagnetic radiation energy, it would introduce more jitter to the display signal within the active time of display signal transmission. Accordingly, this spread spectrum method reduces the accuracy of the display signal and increases the processing difficulty of the display signal. Moreover, in order to avoid the situation where the frequency jitter affects the display signal too much and thus hinders the normal transmission and processing of the display signal, the amplitude of the data rate change brought by spread spectrum usually cannot exceed 3% of the transmission data rate of the display signal. Due to the small variation in data rate caused by this spread spectrum method, the waveforms in various states of the display signal (for example, it may include eight states of 000, 001, 010, 011, 100, 101, 110 and 111) could be repeatedly superimposed by an oscilloscope to form an eye diagram corresponding to the display signal. Assuming that the eye diagram corresponding to the display signal when spread spectrum is not performed is as shown in
Therefore, the present disclosure provides a signal transmission method for a display device, which could effectively reduce Electro Magnetic Interference of the display device without introducing disturbance to the display signal of the display device.
As an example, the present disclosure relates to the technology for reducing Electro Magnetic Interference of the display device, and embodiments of the present disclosure will be further described below with reference to the drawings.
Generally, for a display device based on a point-to-point transmission architecture, the signal transmission period of the display device includes a blanking time and an active time.
More specifically, in the scanning process where the display device converts the electrical signal into the optical signal, for example, the scanning may start from the upper left corner of the display screen and move horizontally to the right, and when the scanning point moves to the rightmost side of the display screen, the scanning point quickly returns to the leftmost side and starts scanning the next line again. The time between the scanning point moving from the rightmost side of the N-th line to the leftmost side of the (N+1)-th line is called the horizontal blanking (H-Blank) time, where N is a positive integer. The scanning point returns to the upper left corner of the display screen after scanning of all the lines (i.e., scanning point reaches the bottom right corner of the display screen), to prepare for the next scanning (that is, the next frame). The time between the scanning point moving from the bottom right corner of the display screen to the upper left corner of the display screen is called the vertical blanking (V-Blank) time.
It could be seen that the display signal of the display device is actually transmitted only within the active time, and the blanking time is used to prepare for transmission of the display signal. Therefore, the present disclosure provides a signal transmission method for a display device, including: adjusting a data rate for signal transmission within a blanking time; and performing signal transmission within an active time by using the data rate adjusted within the blanking time. Because the adjusted data rate is used for signal transmission within the active time (that is, the data rate used for signal transmission is not adjusted within the active time), the jitter of display signal transmission could be reduced and the transmission quality of display signal could be improved.
Taking a line period as the signal transmission period and a horizontal blanking time as the blanking time,
In
Similarly, taking a frame period as the signal transmission period and a vertical blanking time as the blanking time,
In
It should be noted that the signal transmission method of the present disclosure could adjust the data rate for signal transmission only within the horizontal blanking time, could also adjust the data rate for signal transmission only within the vertical blanking time, and could also adjust the data rate for signal transmission within both the horizontal blanking time and the vertical blanking time.
Different from the spread spectrum method in which the UI is the basic unit of jitter, the signal transmission method in the embodiments shown in
It should be understood that for the signal transmission method for a display device of the present disclosure, the variation in data rate for signal transmission is high, thus the corresponding eye diagram cannot be obtained by repeatedly superimposing the waveforms in various states of the display signal, that is, the image shown in
As shown in
For a plurality of frames, the data rate for signal transmission may be adjusted within every frame period; optionally, the frame period may be selected at a fixed interval to adjust the data rate for signal transmission (for example, the data rate for signal transmission is adjusted every two frame periods); optionally, the frame period may be randomly selected to adjust the data rate for signal transmission; optionally, the frame period may be selected in real time according to other parameters of the circuit to adjust the data rate for signal transmission.
For example, in
According to the embodiment of the present disclosure, for a plurality of frame periods, the data rate for signal transmission may also be adjusted periodically. For example, the data rate for signal transmission may be adjusted with a first number of frame periods as an adjustment cycle period, such that the data rate changes periodically within the adjustment cycle period, and a second number of frame periods is taken as a maintaining time, and signal transmission is performed at the same data rate within the maintaining time, where the first number and the second number are integers, and the first number is greater than the second number.
For example, the data rate for signal transmission may be adjusted with 11 frame periods (that is, the first number of frame periods) as the adjustment cycle period, such that the data rate changes periodically within the adjustment cycle period, and one or more (for example, 2, 3, 5, etc.) frame periods (that is, the second number of frame periods) may be taken as the maintaining time, and signal transmission is performed at the same data rate within the maintaining time, where the number of frame periods within the maintaining time is less than 11.
For another example, 24 frame periods (that is, the first number of frame periods) are taken as the adjustment cycle period, the data rate is adjusted once every 4 frame periods, that is, the maintaining time of each data rate is 4 frame periods (that is, the second number of frame periods). Specifically, the data rate of the first to fourth frame periods is f1, the data rate of the fifth to eighth frame periods is f2, the data rate of the ninth to twelfth frame periods is f3, the data rate of the thirteenth to sixteenth frame periods is f4, the data rate of the seventeenth to twentieth frames is f3, the data rate of the twenty-first to twenty-fourth frames is f2, and the data rate of the twenty-fifth to twenty-eighth frames becomes f1 again.
Optionally, for the frame period in which the data rate for signal transmission needs to be adjusted, the adjusted data rate may be determined based on a current data rate according to a predetermined adjustment rule (for example, monotonically increasing or decreasing a certain proportion). For example, the data rate may monotonically increase with a first step size in a first part of an adjustment cycle period and monotonically decrease with a second step size in a second part of the adjustment cycle period, the first step size may be the same as or different from the second step size.
In addition, for the frame period in which the data rate for signal transmission needs to be adjusted, the adjusted data rate may also be randomly determined.
It should be understood that, similar to the embodiment shown in
In addition, for a plurality of line periods, the data rate for signal transmission may also be adjusted periodically. For example, the data rate for signal transmission may be adjusted with a third number of line periods as an adjustment cycle period, such that the data rate changes periodically within the adjustment cycle period, and a fourth number of line periods is taken as a maintaining time, and signal transmission is performed at the same data rate within the maintaining time, where the third number and the fourth number are integers, and the third number is greater than the fourth number.
Optionally, for the line period in which the data rate for signal transmission needs to be adjusted, the adjusted data rate may be determined based on a current data rate according to a predetermined adjustment rule (for example, monotonically increasing or decreasing by a certain proportion). For example, the data rate may monotonically increase with a first step size in a first part of an adjustment cycle period and monotonically decrease with a second step size in a second part of the adjustment cycle period, the first step size may be the same as or different from the second step size.
For example, 20 line periods (that is, the third number of line periods) may be used as the adjustment cycle period, and the data rate may be adjusted once every 5 line periods (that is, the fourth number of line periods), that is, the maintaining time of each data rate is 5 line periods. Specifically, the data rate of the first to fifth line periods is f1, the data rate of the sixth to tenth line periods is f2, and the data rate of the eleventh to fifteenth line periods is f3, the data rate of the sixteenth to twentieth line periods is f2, and then the data rate of the twenty-first to twenty-fifth frame periods becomes f1 again.
In addition, the adjusted data rate may also be determined randomly for the line period where the data rate for signal transmission needs to be adjusted.
According to the embodiment of the present disclosure, the time length of the frame period and/or the line period may be fixed. The length of the line active time is associated with the adjusted data rate. The length of the horizontal blanking time may be determined by the line period and the length of the active time. For example, horizontal blanking time=line period−line active time.
In the example of
For the example shown in
As shown in
In the example of
For the example shown in
Similarly, according to the embodiment of the present disclosure, the data rate may also be adjusted based on the frame period as shown in
In the example of
For the example shown in
Similarly, according to the embodiment of the present disclosure, the data rate may also be adjusted based on the frame period as shown in
In the example of
For the example shown in
Similarly, according to the embodiment of the present disclosure, the data rate may also be adjusted based on the frame period as shown in
For the signal transmission method of the present disclosure, both the data rate within the line period and the data rate within the frame period could be changed randomly.
For example, assuming that the data rate within the active time of the N-th line is f, the data rate within the active time of the (N−a)-th line may be f±c%, and the data rate within the active time of the (N+b)-th line may be f±d%, where a, b are the number of lines differ from the N-th line, c, d are the variation amplitude of the data rate, and further, a, b may be the same or different values, c, d may be the same or different values.
For another example, assuming that the data rate within the active time of the M-th frame is f, the data rate within the active time of the (M−x)-th frame may be f±w%, and the data rate within the active time of the (M+y)-th frame may be f±z%, where x, y are the number of frames different from the M-th frame, w, z are the variation amplitude of the data rate, and further, x, y may be the same or different values, w, z may be the same or different values.
By randomly changing the data rate within the data transmission range that the receiving end could process, the signal transmission method of the present disclosure could be used in more abundant application scenarios, to meet more abundant data rate change requirements.
In step S901, a data rate for signal transmission is adjusted within a blanking time; in step S902, signal transmission is performed within an active time by using the data rate adjusted within the blanking time, where a signal transmission period of the display device may include the blanking time and the active time.
According to embodiments of the present disclosure, the signal transmission period may be a frame period, the blanking time may be a vertical blanking time, and the data rate for signal transmission may be adjusted within the vertical blanking time, where the adjusted data rate is used for performing signal transmission within at least one frame after the vertical blanking time or used for performing signal transmission within at least one line after the vertical blanking time.
Optionally, a first number of frame periods may be taken as an adjustment cycle period, the data rate used for signal transmission is adjusted, such that the data rate changes periodically within the adjustment cycle period, a second number of frame periods is taken as a maintaining time, and signal transmission is performed at the same data rate within the maintaining time, where the first number and the second number are integers, and the first number is greater than the second number.
According to embodiments of the present disclosure, the signal transmission period may be a line period, the blanking time may be a horizontal blanking time, and the data rate for signal transmission may be adjusted within the horizontal blanking time, where the adjusted data rate is used for performing signal transmission within at least one line after the horizontal blanking time.
Optionally, a third number of line periods may be taken as an adjustment cycle period, the data rate used for signal transmission is adjusted, such that the data rate changes periodically within the adjustment cycle period, a fourth number of line periods is taken as a maintaining time, and signal transmission is performed at the same data rate within the maintaining time, where the third number and the fourth number are integers, and the third number is greater than the fourth number.
The line period may have a preset time length, and a length of the active time is associated with the adjusted data rate; and a length of the horizontal blanking time is determined by the line period and the length of the active time.
According to the embodiment of the present disclosure, an amount of data rate change within the adjustment cycle period is less than or equal to a first threshold, and an amount of data rate change between two adjacent data rates is less than or equal to a second threshold, wherein the first threshold is greater than or equal to the second threshold. For example, the first threshold may be 25% of a reference data rate, and the second threshold may be 5% of the reference data rate. The first threshold and the second threshold may be determined according to the actual demand or the performance of the display device hardware. According to the embodiment of the present disclosure, the first threshold and the second threshold may be determined by a maximum allowable data rate and a minimum allowable data rate of the display device hardware, where the maximum allowable data rate is determined by the data receiving/processing capability of the receiving end for signal transmission, and the minimum allowable data rate is determined by the length of the active time and the amount of data to be transmitted.
According to embodiments of the present disclosure, the data rate may monotonically increase in a first part of the adjustment cycle period and monotonically decrease in a second part of the adjustment cycle period, where the data rate is lower than a maximum allowable data rate at a receiving end for signal transmission.
In addition, both the moment for adjusting signal transmission and the data rate for signal transmission may be determined in a random manner. That is, for a plurality of consecutive signal transmission periods of the display device, at least one signal transmission period for adjusting the data rate for signal transmission may be randomly determined. And for each signal transmission period of the display device, it may be further randomly determined whether to adjust the data rate for signal transmission. It should be understood that the signal transmission period herein may be either a frame period or a line period.
For each signal transmission period of the display device, when it is determined that the data rate for signal transmission needs to be adjusted, the adjusted data rate is determined based on a current data rate according to a predetermined adjustment rule (for example, the adjusted data rate may be determined by multiplying the current data rate by a certain proportional coefficient, and the adjusted data rate may be determined by increasing or decreasing the current data rate by a certain value, etc.); or the adjusted data rate is randomly determined.
As shown in
Optionally, the signal transmission period may be a frame period, and the blanking time may be a vertical blanking time. In this case, the rate adjustment circuit 1010 may be further configured to adjust the data rate for signal transmission within the vertical blanking time, where the adjusted data rate is used for performing signal transmission within at least one consecutive frame after the vertical blanking time or used for performing signal transmission within at least one consecutive line after the vertical blanking time.
Optionally, the signal transmission period may be a line period, and the blanking time may be a horizontal blanking time. In this case, the rate adjustment circuit 1010 may be further configured to adjust the data rate for signal transmission within the horizontal blanking time, where the adjusted data rate is used for performing signal transmission within at least one consecutive line after the horizontal blanking time.
According to the embodiment of the present disclosure, the rate adjustment circuit 1010 could either adjust the data rate for signal transmission periodically or adjust the data rate for signal transmission randomly.
For example, in the case where the rate adjustment circuit 1010 adjusts the data rate for signal transmission periodically, the data rate may monotonically increase in a first part of an adjustment cycle and monotonically decrease in a second part of the adjustment cycle, where the data rate is lower than a maximum allowable data rate of the receiving end for signal transmission. Optionally, the data rate may monotonically increases at a first step size, and monotonically decreases at a second step size, where the first step size is the same as or different from the second step size.
In the case where the rate adjustment circuit 1010 adjusts the data rate for signal transmission randomly, the rate adjustment circuit 1010 may be further configured to, for a plurality of consecutive signal transmission periods of the display device, randomly determine at least one signal transmission period for adjusting the data rate for signal transmission. In addition, the rate adjustment circuit 1010 may also be configured to, for each signal transmission period of the display device, randomly determine whether to adjust the data rate for signal transmission. Optionally, for each signal transmission period of the display device, when it is determined that the data rate for signal transmission needs to be adjusted, the adjusted data rate may be determined based on a current data rate according to a predetermined adjustment rule; or the adjusted data rate may be determined randomly.
Embodiments of the present disclosure further provide a display device, which may include the signal transmission apparatus in any of the embodiments described above, and transmit a display signal by the signal transmission method in any of the embodiments described above. Optionally, the display device of the present disclosure may include various devices including a display screen, such as mobile phones, computers, game consoles, projectors, etc. The display device of the present disclosure may be based on a point-to-point transmission architecture.
Therefore, the present disclosure provides a signal transmission method and apparatus for a display device, and a display device.
According to the embodiment of the present disclosure, the signal transmission method for a display device comprising: adjusting a data rate for signal transmission within a blanking time; and performing signal transmission within an active time by using the data rate adjusted within the blanking time; where a signal transmission period of the display device includes the blanking time and the active time.
Since the present disclosure adjusts the data rate for signal transmission within the blanking time and performs signal transmission within the active time by using the data rate adjusted within the blanking time, it not only reduces the Electro Magnetic Interference during signal transmission, but also prevents frequency variations from affecting the quality of the picture displayed by the display device, thus improving the overall performance of the display device. Furthermore, since the data rate used for signal transmission is adjusted within the blanking time, it is possible to significantly expand the range of data rate used for signal transmission, so as to meet more abundant data rate transmission requirements. This also allows for a more even distribution of electromagnetic radiation energy across a wider bandwidth frequency range, further enhancing the effectiveness of reducing electromagnetic interference during signal transmission.
It should be noted that, although the above embodiments of the present disclosure mainly take the display device based on a point-to-point transmission architecture as an example, the data rate adjustment manner of the present disclosure may also be applied to the display device with a Multi-drop transmission architecture (for example, the Mini-LVDS (Low Voltage Differential Signaling) transmission architecture). That is, in the case of a display device with the Mini-LVDS transmission architecture, the data rate for signal transmission may also be adjusted in order to expand the range of data rate for signal transmission, such that the energy of electromagnetic radiation could be evenly distributed across a wider bandwidth frequency range, thus reducing Electro Magnetic Interference during signal transmission.
For the Mini-LVDS transmission architecture, since the data signal and the clock signal are transmitted independently, there is no need to distinguish the active time and the blanking time for transmission, as long as the data signal and the clock signal are synchronously adjusted.
Therefore, under the Mini-LVDS transmission architecture, it is not necessary to adjust the data rate for signal transmission within the blanking time as that in the point-to-point architecture, and it could be still ensured that the variation of data rate will not affect the quality of the picture displayed by the display device. Optionally, the data rate for signal transmission may be adjusted by the following manners and any combinations thereof: adjusting the data rate for signal transmission in units of a frame period, adjusting the data rate for signal transmission in units of a line period, and adjusting the data rate for signal transmission in units of a unit interval (UI). In addition, the data rate for signal transmission may also be adjusted within a frame and/or within a line. Under the Mini-LVDS transmission architecture, by controlling the specifications of the respective eye diagrams (similar to that shown in
The present disclosure uses specific words to describe the embodiments of the present disclosure. Examples such as “first/second embodiment”, “one embodiment” and/or “some embodiments” refer to a certain feature, structure or characteristic related to at least one embodiment of the present disclosure. Therefore, it should be emphasized and noted that “an embodiment” or “one embodiment” or “an alternative embodiment” mentioned twice or more in different places in this specification do not necessarily mean the same embodiment. In addition, some features, structures, or characteristics in one or more embodiments of the present disclosure may be appropriately combined.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having the meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.
The data signal Sd and the clock signal Sck may be transmitted by differential signaling, and the data line Ld and the clock line Lck may be differential pairs of transmitting the data signal Sd and the clock signal Sck, respectively. The data signal Sd may carry pixel data. The source drivers 121 to 126 may be further coupled to a display panel including a plurality of columns of pixels, and each of the source drivers 121 to 126 may be coupled to predetermined columns of pixels. For example, the display panel may have a full high definition (FHD) resolution including 1920 columns of pixels, each column of pixels including 1080 lines. The source driver 121 may be coupled to the first to 320th columns of pixels, the source driver 122 may be coupled to the 321st to 640th columns of pixels, . . . , and the source driver 126 may be coupled to the 1601st to 1920th columns of pixels, so as to drive the pixel data to the 1920 columns of pixels. The source driver 121 may sample and drive the pixel data to the first to 320th columns of pixels in a first duration, the source driver 122 may sample and drive the pixel data to the 321st to 640th columns of pixels in a second duration, . . . , and the source driver 126 may sample and drive the pixel data to the 1601st to 1920th columns of pixels in a sixth duration, the first duration to the sixth duration being adjacent in sequence.
The data rate may match the clock rate. In some embodiments, the data rate may be equal to the clock rate. For example, if the data rate is 600 megahertz (MHz), the clock rate will be 600 megahertz (MHz). Since the data signal Sd and the clock signal Sck are generated at varying identical rates, the electromagnetic interference may be evenly spread out over the spectrum of the varying rates, effectively reducing the electromagnetic interference, reducing the total jitter, reducing the data loss and enhancing the data security.
In Step S1302, the controller 120 sets a data rate cycle during which the data rate of the data signal Sd and the clock rate of the clock signal Sck are varied periodically. The data rate cycle may include a set of time intervals equal or unequal in length. For example, each time interval in the data rate cycle may have a length of 1 line. In another example, a time interval in the data rate cycle may have a length of 2 lines, another time interval in the data rate cycle may have a length of 5 lines, and yet another time interval in the data rate cycle may have a length of 10 lines. In some embodiments, the set of time intervals may include a first time interval, a second time interval and a third time interval, the first time interval, the second time interval and the third time interval being non-overlapping with each other. In some embodiments, the first time interval, the second time interval and the third time interval may be adjacent in sequence.
In Step S1304, the source drivers 121 to 126 simultaneously receive a first data signal generated at a first data rate from the controller 120 via the data line Ld and receive a first clock signal at a first clock rate from the controller 120 via the clock line Lck in the first time interval. That is, the source drivers 121 to 126 receive the first data signal via the data line Ld while receiving the first clock signal via the clock line Lck in the first time interval.
In Step S1306, the source drivers 121 to 126 simultaneously receive a second data signal generated at a second data rate from the controller 120 via the data line Ld and receive a second clock signal at a second clock rate from the controller 120 via the clock line Lck in the second time interval. That is, the source drivers 121 to 126 receive the second data signal via the data line Ld while receiving the second clock signal via the clock line Lck in the second time interval.
In Step $1308, the source drivers 121 to 126 simultaneously receive a third data signal generated at a third data rate from the controller 120 via the data line Ld and receive a third clock signal at a third clock rate from the controller 120 via the clock line Lck in the third time interval. That is, the source drivers 121 to 126 receive the third data signal via the data line Ld while receiving the third clock signal via the clock line Lck in the third time interval.
The data signal Sd may include the first data signal, the second data signal and the third data signal, and the data rate may include the first data rate, the second data rate and the third data rate, the first data rate, the second data rate and the third data rate being different from each other. Similarly, the clock signal Sck may include the first clock signal, the second clock signal and the third clock signal, and the clock rate may include the first clock rate, the second clock rate and the third clock rate, the first clock rate, the second clock rate and the third clock rate matching the first data rate, the second data rate and the third data rate, respectively. In some embodiments, the first data rate may be equal to the first clock rate, the second data rate may be equal to the second clock rate, and the third data rate may be equal to the third clock rate.
In general, the larger the difference between the data rates of two adjacent time intervals is, the less the interference is. For example, a difference of 50 MHz between the first data rate and the second data rate may result in less interference than a difference of 5 MHz between the first data rate and the second data rate. The data rate cycle may be line-based. During a data rate cycle, the source drivers 121 to 126 may receive a first number of frames, and during each time interval of the set of time intervals in the data rate cycle, the source drivers 121 to 126 may receive a second number of frames. The first number and the second number may be positive integers, and the first number may exceed the second number. For example, if the first number may be 21 and the second number may be 1, the source drivers 121 to 126 may receive 21 frames in each data rate cycle, and receive 1 frame in each time interval, as illustrated in
In
In
In
In some embodiments, the first data rate f−w% and the second data rate f differ by a non-zero fixed difference w%, and the second data rate f and the third data rate (f+z%) differ by the non-zero fixed difference z%, that is, w=z. For example, f=870 MHz, w%=z%=5%, the first data rate is 827 MHz (=870−870*5%), the second data rate is 870 MHz, and the third data rate is 914 MHz (=870+870*5%).
In other embodiments, the first data rate f−w% and the second data rate f differ by a first non-zero random difference w%; and the second data rate f and the third data rate (f+z%) differ by a second non-zero random difference z%, that is, w≠z. For example, f=870 MHz, w%=8% and z%−6%, the first data rate is 800 MHz (=870−870*8%), the second data rate is 870 MHz, and the third data rate is 922 MHz (=870+870*6%).
Since each time interval starts at the vertical blanking interval VB of a frame (e.g., t2 starts at VB), the data signal Sd may have sufficient time (e.g., from t2 to the start of AF) to stabilize before receiving active video data in the active video interval AF of the frame.
In
In some embodiments, the first data rate f−w% and the second data rate f differ by a non-zero fixed difference w%, and the second data rate f and the third data rate (f+z%) differ by the non-zero fixed difference z%, that is, w=z. For example, f=870 MHz, w%=z%=5%, the first data rate is 827 MHz (=870−870*5%), the second data rate is 870 MHz, and the third data rate is 914 MHz (=870+870*5%).
In other embodiments, the first data rate f−w% and the second data rate f differ by a first non-zero random difference w%; and the second data rate f and the third data rate (f+z%) differ by a second non-zero random difference z%, that is, w≠z. For example, f=870 MHz, w%=8% and z%=6%, the first data rate is 800 MHz (=870−870*8%), the second data rate is 870 MHz, and the third data rate is 922 MHz (=870+870*6%).
Since each time interval starts at the active video interval AF of a frame, the controller 120 may have more flexibility to change the data rate of the data signal Sd.
For the line-based data rate cycle, the data rate cycle and each time interval in the data rate cycle are measured by rows. During the line-based data rate cycle, the source drivers 121 to 126 may receive a first number of rows, and during each time interval of the set of time intervals in the line-based data rate cycle, the source drivers 121 to 126 may receive a second number of rows. The first number and the second number may be positive integers, and the first number may exceed the second number. For example, if the first number may be 21 and the second number may be 1, the source drivers 121 to 126 may receive 21 lines in the data rate cycle, and receive 1 line in each time interval. In another example, if the first number may be 20 and the second number may be 2, the source drivers 121 to 126 may receive 20 lines in the data rate cycle, and receive 2 lines in each time interval.
In
In some embodiments, the first data rate f−w% and the second data rate f differ by a non-zero fixed difference w%, and the second data rate f and the third data rate (f+z%) differ by the non-zero fixed difference z%, that is, w=z. For example, f=870 MHz, w%=z%=5%, the first data rate is 827 MHz (=870−870*5%), the second data rate is 870 MHz, and the third data rate is 915 MHz (=870+870*5%).
In other embodiments, the first data rate f−w% and the second data rate f differ by a first non-zero random difference w%; and the second data rate f and the third data rate (f+z%) differ by a second non-zero random difference z%, that is, w≠z. For example, f=870 MHz, w%=8% and z%=6%, the first data rate is 800 MHZ (=870−870*8%), the second data rate is 870 MHz, and the third data rate is 922 MHz (=870+870*6%).
Since each time interval starts at the horizontal blanking interval HB of a row (e.g., t2 starts at HB), the data signal Sd may have sufficient time (e.g., from t2 to the start of AL) to stabilize before receiving active video data in the active video interval AL of the row.
In
In some embodiments, the first data rate f−w% and the second data rate f differ by a non-zero fixed difference w%, and the second data rate f and the third data rate (f+z%) differ by the non-zero fixed difference z%, that is, w=z. For example, f=870 MHz, w%=z%=5%, the first data rate is 827 MHz (=870−870*5%), the second data rate is 870 MHz, and the third data rate is 915 MHz (=870+870*5%).
In other embodiments, the first data rate f−w% and the second data rate f differ by a first non-zero random difference w%; and the second data rate f and the third data rate (f+z%) differ by a second non-zero random difference z%, that is, w≠z. For example, f=870 MHz, w%=8% and z%=6%, the first data rate is 800 MHz (=870−870*8%), the second data rate is 870 MHz, and the third data rate is 922 MHz (=870+870*6%).
Since each time interval starts at the active video interval AL of a row, the controller 120 may have more flexibility to change the data rate of the data signal Sd.
At Time t1, a first pulse occurs in the vertical start pulse signal STV, indicating the start of a frame F(n). Between Time t1 and Time t2, the data of the frame F(n) is transmitted on the data signal Sd at a first data rate. At Time t2, a second pulse occurs in the vertical start pulse signal STV, indicating the start of a frame F(n+1). Between Time t2 and Time t3, the data of the frame F(n+1) is transmitted on the data signal Sd at a second data rate. At Time t3, a third pulse occurs in the vertical start pulse signal STV, indicating the start of a subsequent frame. The first data rate is different from the second data rate, thereby reducing the electromagnetic interference, reducing the total jitter, reducing the data loss and enhancing the data security.
Between Time t1 and Time t2, the data of the row L(n−1) is transmitted on the data signal Sd at a first data rate.
Between Time t2 and Time t3, the data of the row L(n) is transmitted on the data signal Sd at a second data rate.
Between Time t3 and Time t4, the data of the row L(n+1) is transmitted on the data signal Sd at a third data rate. The first data rate, the second data rate and the third data rate are different from each other, thereby reducing the electromagnetic interference, reducing the total jitter, reducing the data loss and enhancing the data security.
In the point-to-point architecture in
In Step S1902, the timing controller T-CON varies the data rates of pixel packets across a set of lines in the active area on a per-line basis, either by increasing or decreasing the data rate within a predetermined rate range. The predetermined rate range may be computed based on a first proportion of a center data rate, e.g., ±25% of the center data rate. For example, if the center data rate is 870 Mbps, the predetermined rate range spans from 653 Mbps (=870*0.75) to 1088 Mbps (=870*1.25). In some embodiments, the increase or decrease in the data rate may occur unidirectionally by a constant amount determined as a second proportion of the center data rate in the predetermined rate range. The constant amount may be less than a predetermined limit, e.g., 100 Mbps, to improve the success rate of achieving clock synchronization at the source driver SD. For example, referring to
In Steps S1904 and S1906, the source driver SD monitors the data rate of a pixel packet in the active area of a frame and synchronizes the clock of the source driver SD according to the data rate of the pixel packet to generate a synchronized clock.
The format of the pixel packet is illustrated in
In Step S1908, the source driver SD determines whether the clock is locked after the clock synchronization. Since the clock is locked, the source driver SD clocks the payload data of the pixel packet P(M) in the line L(n) using the synchronized clock (S1910). If the clock is unlocked, the source driver SD may signal the timing controller T-CON to indicate that synchronization has been lost. In response, the timing controller T-CON may transmit a clock training pattern to the source driver SD, prompting the source driver SD to perform clock training (Step S1912). Subsequently, the source driver SD determines whether the clock is locked (Step S1908). Steps S1912 and S1908 are iterated in loops until the clock achieve synchronization. Once locked, the payload data of pixel packets can be generated using the synchronized clock.
Likewise, Steps S1902 to 1910 may be used to transmit the pixel packet P(1) in the line L(n+1) at a data rate different from the pixel packet P(M) in the line L(n). In Step S1902, the timing controller T-CON varies the data rate of the pixel packet P(1) in the line L(n+1). In Steps S1904 and S1906, the source driver SD identifies a delimiter pulse from the delimiter field Dlimt(1) of a pixel packet P(1) in the line L(n+1) to monitor the data rate of the pixel packet P(1) in the line L(n+1). The source driver SD detects a clock edge (falling edge) at Time t5 and another clock edge (rising edge) at Time t6, thereby identifying the phase t5 and the width UI(1)(=t6−t5) of the delimiter pulse of a pixel packet P(1). Subsequently, the source driver SD computes the inverse of the width UI(1) to estimate the data rate of the pixel packet P(1). Since the width UI(1) is different from the width UI(M), the data rate of the pixel packet P(1) is different from the data rate of the pixel packet P(M). Further, the source driver SD synchronizes the clock by adjusting the phase of the clock according to the phase t5 of the delimiter pulse of the pixel packet P(1) and the frequency of the clock according to the data rate of the pixel packet P(1). Between Time t7 and Time t8, the source driver SD receives the first bit of the payload data in the payload field Dpx(1) of the pixel packet P(1), and in Step S1908, the source driver SD determines whether the clock is locked after the clock synchronization. Each bit in the payload field Dpx(1) have the length of 1 UI(1). Since the clock is locked, the source driver SD clocks the payload data of the pixel packet P(1) in the line L(n+1) using the synchronized clock (S1910).
At Time t1, the timing controller T-CON switches the clock signal Tx CLK from 696 Mbps to 740 Mbps, generating the pixel packets in the line L(N) of the frame F(p) for transmission on the data signal Ld. Thus, the line L(N) of the frame F(p) has a data rate of “740 Mbps”. Simultaneously, the timing controller T-CON transmits a pulse psw1 in the frequency switching signal Fsw to the source drivers SD. Between Time t1 and Time t2, the pulse psw1 occurs in the frequency switching signal Fsw, initiating a transition in the clock signal SD CLK from 696 Mbps to 740 Mbps according to the data rate “740 Mbps” of the line L(N), thereby synchronizing the clock signal SD CLK to the clock signal Tx CLK. The source drivers SD acquire the pixel packets in the line L(N) of the frame F(p) based on the update frequency “740 Mbps” of the clock signal SD CLK. At Time t3, the source drivers SD complete reception of the pixel packets in the line L(N−1) of the frame F(p). Between Time t3 and Time t4, a pulse pd1 occurs in the load signal LD, prompting the source drivers SD to convert the line L(N−1) from digital to analog, resulting in the generation of the line L′(N−1) in the output signal Output. The frequency of the clock signal SD CLK remains at 740 Mbps between Time t2 and Time t5. The lock signal SD lock remains at the logic “1” between Time t1 and Time t5, signifying that the clock signal SD CLK is synchronized.
At Time t5, the timing controller T-CON switches the clock signal Tx CLK from 740 Mbps to 783 Mbps, generating the pixel packets in the dummy line Post-DE1 of the frame F(p) for transmission on the data signal Ld. Thus, the dummy line Post-DE1 of the frame F(p) has a data rate of “783 Mbps”. Simultaneously, the timing controller T-CON transmits a pulse psw2 in the frequency switching signal Fsw to the source drivers SD. The pulse psw2 initiates a transition in the clock signal SD CLK from 740 Mbps to 783 Mbps according to the data rate “783 Mbps” of the dummy line Post-DE1, thereby synchronizing the clock signal SD CLK to the clock signal Tx CLK. The source drivers SD acquire the pixel packets in the dummy line Post-DE1 of the frame F(p) based on the update frequency “783 Mbps” of the clock signal SD CLK. At Time t6, the source drivers SD complete reception of the pixel packets in the line L(N) of the frame F(p), and a pulse pd2 occurs in the load signal LD, prompting the source drivers SD to convert the line L(N) from digital to analog, resulting in the generation of the line L′(N) in the output signal Output. The clock signal SD CLK maintains the frequency of 783 Mbps up until Time t7. The lock signal SD lock remains at the logic “1” between Time t5 and Time t7, signifying that the clock signal SD CLK is synchronized.
At Time t7, the timing controller T-CON switches the clock signal Tx CLK from 783 Mbps to 827 Mbps, generating the pixel packets in the dummy line Post-DE2 of the frame F(p) for transmission on the data signal Ld. Thus, the dummy line Post-DE2 of the frame F(p) has a data rate of “827 Mbps”. Simultaneously, the timing controller T-CON transmits a pulse psw3 in the frequency switching signal Fsw to the source drivers SD. The pulse psw3 initiates a transition in the clock signal SD CLK from 783 Mbps to 827 Mbps according to the data rate “827 Mbps” of the dummy line Post-DE2, thereby synchronizing the clock signal SD CLK to the clock signal Tx CLK. The source drivers SD acquire the pixel packets in the dummy line Post-DE2 of the frame F(p) based on the update frequency “827 Mbps” of the clock signal SD CLK. At Time t8, the source drivers SD complete reception of the pixel packets in the dummy line Post-DE1 of the frame F(p), and a pulse pd3 occurs in the load signal LD, prompting the source drivers SD to convert the dummy line Post-DE1 from digital to analog, resulting in the generation of the dummy line Post-DE1′ in the output signal Output. The frequency of the clock signal SD CLK maintains the frequency of 827 Mbps up until Time t9. The lock signal SD lock remains at the logic “1” between Time t7 and Time t9, signifying that the clock signal SD CLK is synchronized.
At Time t9, the timing controller T-CON switches the clock signal Tx CLK from 827 Mbps to 870 Mbps, generating the pixel packets in the dummy line Post-DE3 of the frame F(p) for transmission on the data signal Ld. Thus, the dummy line Post-DE3 of the frame F(p) has a data rate of “870 Mbps”. Simultaneously, the timing controller T-CON transmits a pulse psw4 in the frequency switching signal Fsw to the source drivers SD. The pulse psw4 initiates a transition in the clock signal SD CLK from 827 Mbps to 870 Mbps according to the data rate “870 Mbps” of the dummy line Post-DE3, thereby synchronizing the clock signal SD CLK to the clock signal Tx CLK. The source drivers SD acquire the pixel packets in the dummy line Post-DE3 of the frame F(p) based on the update frequency “870 Mbps” of the clock signal SD CLK. At Time t10, the source drivers SD complete reception of the pixel packets in the dummy line Post-DE2 of the frame F(p), and a pulse pd4 occurs in the load signal LD, prompting the source drivers SD to convert the dummy line Post-DE2 from digital to analog, resulting in the generation of the dummy line Post-DE2′ in the output signal Output. The frequency of the clock signal SD CLK maintains the frequency of 870 Mbps up until Time t11. The lock signal SD lock remains at the logic “1” between Time t9 and Time t11, signifying that the clock signal SD CLK is synchronized.
At Time t11, the timing controller T-CON switches the clock signal Tx CLK from 870 Mbps to 696 Mbps, generating the pixel packets in a line of the frame F(p+1) for transmission on the data signal Ld. Simultaneously, the timing controller T-CON transmits a pulse psw5 in the frequency switching signal Fsw to the source drivers SD. The pulse psw5 attempts to initiate a transition in the clock signal SD CLK from 870 Mbps to 696 Mbps. However, the clock signal SD CLK fails to achieve synchronization to 696 Mbps, and consequently the frequency of the clock signal SD CLK is reduced to 0 Mbps, leading to the logic “0” in the lock signal SD lock. After Time t11, the source driver SD continues to synchronize the clock signal SD CLK to the clock signal Tx CLK according to the data rate “696 Mbps” of the training clock CT. At Time t12, the source driver SD successfully synchronizes the clock signal SD CLK to the clock signal Tx CLK, achieving the frequency 696 Mbps. Once the clock signal SD CLK is synchronized, the lock signal SD lock switches from the logic “0” to the logic “1”. Due to the clock signal SD CLK being out of synchronization, the source drivers SD are unable to decode the pulse in the load signal LD that corresponds to the dummy line Post-DE3. Consequently, the dummy line Post-DE2′ remains in the output signal OUTPUT between Time t11 and Time t18. At Time t13, the timing controller T-CON sends a pulse psw6 in the frequency switching signal Fsw to the source drivers SD. The pulse psw6 initiates a transition in the clock signal SD CLK from 696 Mbps to 653 Mbps according to the clock training pattern CT of “653 Mbps”, thereby synchronizing the clock signal SD CLK. The frequency of the clock signal SD CLK is synchronized to 635 Mbps. Consequently, the lock signal SD lock remains at the logic “1” between Time t13 and Time t15, signifying that the clock signal SD CLK is synchronized.
At Time t15, the timing controller T-CON switches the clock signal Tx CLK from 653 Mbps to 696 Mbps, generating the pixel packets in the dummy line Pre-DE1 of the frame F(p+1) for transmission on the data signal Ld. Thus, the dummy line Pre-DE1 of the frame F(p+1) has a data rate of “696 Mbps”. Simultaneously, the timing controller T-CON transmits a pulse psw7 in the frequency switching signal Fsw to the source drivers SD. The pulse psw7 initiates a transition in the clock signal SD CLK from 653 Mbps to 696 Mbps according to the data rate “696 Mbps” of the dummy line Pre-DE1, thereby synchronizing the clock signal SD CLK to the clock signal Tx CLK. The source drivers SD acquire the pixel packets in the dummy line Pre-DE1 of the frame F(p+1) based on the update frequency “696 Mbps” of the clock signal SD CLK. At Time t16, a pulse pd5 occurs in the load signal LD, enabling the dummy line Post-DE2′ remains in the output signal OUTPUT. The clock signal SD CLK maintains the frequency of 696 Mbps up until Time t17. The lock signal SD lock remains at the logic “1” between Time t15 and Time t17, signifying that the clock signal SD CLK is synchronized.
At Time t17, the timing controller T-CON switches the clock signal Tx CLK from 696 Mbps to 740 Mbps, generating the pixel packets in the line L(1) of the frame F(p+1) for transmission on the data signal Ld. Thus, the line L(1) of the frame F(p+1) has a data rate of “740 Mbps”. Simultaneously, the timing controller T-CON transmits a pulse psw8 in the frequency switching signal Fsw to the source drivers SD. The pulse psw8 initiates a transition in the clock signal SD CLK from 696 Mbps to 740 Mbps according to the data rate “740 Mbps” of the line L(1) of the frame F(p+1), thereby synchronizing the clock signal SD CLK to the clock signal Tx CLK. The source drivers SD acquire the pixel packets in the dummy line Pre-DE1 of the frame F(p) based on the update frequency “740 Mbps” of the clock signal SD CLK. At Time t18, the source drivers SD completes reception of the pixel packets in the dummy line Pre-DE1 of the frame F(p+1), and a pulse pd6 occurs in the load signal LD, prompting the source drivers SD to convert the dummy line Pre-DE1 from digital to analog, resulting in the generation of the dummy line Pre-DE1′ in the output signal Output. The clock signal SD CLK maintains the frequency of 740 Mbps up until Time t19. The lock signal SD lock remains at the logic “1” between Time t17 and Time t19, signifying that the clock signal SD CLK is synchronized.
At Time t19, the timing controller T-CON switches the clock signal Tx CLK from 740 Mbps to 783 Mbps, generating the pixel packets in the line L(2) of the frame F(p+1) for transmission on the data signal Ld. Thus, the line L(2) of the frame F(p+1) has a data rate of “783 Mbps”. Simultaneously, the timing controller T-CON transmits a pulse psw9 in the frequency switching signal Fsw to the source drivers SD. The pulse psw9 initiates a transition in the clock signal SD CLK from 740 Mbps to 783 Mbps according to the data rate “783 Mbps” of the line L(2) of the frame F(p+1), thereby synchronizing the clock signal SD CLK to the clock signal Tx CLK. The source drivers SD acquire the pixel packets in the line L(2) of the frame F(p+1) based on the update frequency “783 Mbps” of the clock signal SD CLK. At Time t20, the source drivers SD completes reception of the pixel packets in the line L(1) of the frame F(p+1), and a pulse pd7 occurs in the load signal LD, prompting the source drivers SD to convert the line L(1) of the frame F(p+1) from digital to analog, resulting in the generation of the line L′(1) in the output signal Output. The clock signal SD CLK maintains the frequency of 783 Mbps after the psw9 is completed. The lock signal SD lock remains at the logic “1”, signifying that the clock signal SD CLK is synchronized.
While
The embodiments in
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
This application is a continuation-in-part of U.S. application Ser. No. 18/370,865, filed on Sep. 20, 2023, which is a continuation-in-part of U.S. application Ser. No. 18/233,006, filed on Aug. 11, 2023, which claims the benefit of U.S. Provisional Application No. 63/408,825, filed on Sep. 21, 2022. The contents of these applications are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63408825 | Sep 2022 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 18370865 | Sep 2023 | US |
| Child | 18744691 | US | |
| Parent | 18233006 | Aug 2023 | US |
| Child | 18370865 | US |
