Number | Date | Country | Kind |
---|---|---|---|
10-113142 | Apr 1998 | JP |
Filing Document | Filing Date | Country | Kind |
---|---|---|---|
PCT/JP99/00586 | WO | 00 |
Publishing Document | Publishing Date | Country | Kind |
---|---|---|---|
WO99/54937 | 10/28/1999 | WO | A |
Number | Name | Date | Kind |
---|---|---|---|
5075577 | Okitaka | Dec 1991 | A |
5099406 | Harada et al. | Mar 1992 | A |
5448198 | Toyoshima | Sep 1995 | A |
5512844 | Nakakura et al. | Apr 1996 | A |
5825206 | Krishnamurthy et al. | Oct 1998 | A |
5889415 | Parkinson | Mar 1999 | A |
6118303 | Schmitt et al. | Sep 2000 | A |
6160417 | Taguchi | Dec 2000 | A |
6255850 | Turner | Jul 2001 | B1 |
6278294 | Taniguchi | Aug 2001 | B1 |
Number | Date | Country |
---|---|---|
3212955 | Sep 1991 | JP |
4267542 | Sep 1992 | JP |
5259289 | Aug 1993 | JP |
653321 | Feb 1994 | JP |
7321293 | Aug 1995 | JP |
8153390 | Nov 1996 | JP |
9162294 | Jun 1997 | JP |
Entry |
---|
Chaterjee et al. (“A low-voltage triggering for on-chip ESD protection at output and input pads”, 1990 Symposium on VLSI Technology, Jun. 4, 1990, pp. 75-76.* |
International Search Report for Application PCT/JP99/00586 mailed Jun. 15, 1999. |