1. Field of the Invention
The present invention relates to a method of driving an anti-ferroelectric liquid crystal display (LCD) panel, and more particularly, to a method for driving an anti-ferroelectric LCD panel having signal electrode lines arranged in parallel above anti-ferroelectric liquid crystal cells, and scan electrode lines arranged in parallel below the anti-ferroelectric liquid crystal cells, perpendicular to the signal electrode lines.
2. Description of the Related Art
Referring to
In the anti-ferroelectric LCD panel 11, signal electrode lines SL1, SL2, SL3, . . . , SLm are arranged in parallel above anti-ferroelectric liquid crystal cells LC, and scan electrode lines CL1, CL2, CL3, . . . , CLn are arranged below the anti-ferroelectric liquid crystal cells LC, perpendicular to the signal electrode lines SL1, SL2, SL3, . . . , SLm. The scan electrode lines CL1, CL2, CL3, . . . , CLn and the signal electrode lines SL1, SL2, SL3, . . . , SLm are formed from a transparent conductor, such as, indium-tin-oxide (ITO).
The driving unit includes a controller 14, a segment driver 12, a modulation signal generator 131, and a common driver 132. The controller 14 processes a video signal Sc received from a host, for example, a notebook computer, and generates a data signal ‘DATA,’ a shift clock signal ‘SCK,’ a frame signal ‘FLM,’ and a latch clock signal ‘LCK.’ The segment driver 12 holds the data signal DATA for the individual signal electrode lines SL1, SL2, SL3, . . . , SLm according to the shift clock signal SCK. In addition, the segment driver 12 applies a signal voltage corresponding to the waiting data signal DATA to the individual signal electrode lines SL1, SL2, SL3, . . . , SLm according to the latch clock signal LCK.
The frame signal FLM indicates the start of a single frame. The modulation signal generator 131 divides the frequency of the latch clock signal LCK to generate a modulation signal. The generated modulation signal controls the polarities of the respective output voltages of the segment driver 12 and the common driver 132.
The common driver 132 sequentially applies a scan voltage to the scan electrode lines CL1, CL2, CL3, . . . , CLn according to the latch clock signal LCK, the frame signal FLM, and the modulation signal. In this manner, light is transmitted through or blocked by individual anti-ferroelectric liquid crystal cells LC in the array.
Referring to
When a voltage applied to the anti-ferroelectric liquid crystal cells LC gradually increases from a ground voltage VG in the negative (−) direction, the anti-ferroelectric liquid crystal cells LC are converted into a negative ferroelectric state at a negative second threshold voltage −Vth2. At this point, external light starts to be transmitted through the anti-ferroelectric liquid crystal cells LC (see the direction denoted by D3). Next, if the negative voltage −V gradually decreases, the negative ferroelectric state is maintained, and the transmission of light continues until the negative voltage −V reaches a negative first threshold voltage −Vth1 (see the direction denoted by D4). Next, when the negative voltage −V becomes lower than the negative first threshold voltage −Vth1, the anti-ferroelectric liquid crystal cells LC are restored to an anti-ferroelectric state, thereby blocking external light.
Referring to
Accordingly, when the first scan selection voltage VCH is applied to one scan electrode line and the selection data voltage VSL is applied to selected signal electrode lines, selected anti-ferroelectric liquid crystal cells LC (shown in
In a second driving step, a second scan selection voltage VCL is sequentially applied to the scan electrode lines CL1, CL2, CL3, . . . , CLn, and simultaneously second display data signals SS1′, SS2′, . . . , SSn′ having voltages VSH and VSL, which have a lower negative level than the second scan selection voltage VCL, are applied to the signal electrode lines SL1, SL2, SL3, . . . , SLm. In addition, while scan is not performed (for example, periods t2′ through tn′ in the waveform diagram S1), a second sustain voltage VCM2, having a lower negative level than the second scan selection voltage VCL and a higher level than the voltages of the second display data signals SS1′, SS2′, . . . SSn,′ is applied to a relevant one among the scan electrode lines CL1, CL2, CL3, . . . , CLn.
Accordingly, when the second scan selection voltage VCL is applied to one scan electrode line and the selection data voltage VSH is applied to selected signal electrode lines, selected anti-ferroelectric liquid crystal cells LC are converted into a negative ferroelectric state. Accordingly, external light begins to be transmitted (refer to the operation corresponding to the D3 direction of
According to such conventional method of driving an anti-ferroelectric liquid crystal display panel, the levels of voltages (VA and VB of
Referring to
Meanwhile, during the sustain period ranging from t2 to t5 following the first scan time t1 in the first frame, while the first scan selection voltage VCH is applied to the other scan electrode lines CL2 through CL5, a voltage applied to the second anti-ferroelectric liquid crystal cell LC has a level VA equal to the sum of the level of the first sustain voltage VCM1, and the level of the logic low voltage VSL, if the logic low voltage VSL is applied to the second signal electrode line SL2, and has a level VB equal to a difference between the level of the first sustain voltage VCM1 and the level of the logic high voltage VSH, if the logic high voltage VSH is applied to the second signal electrode line SL2. Accordingly, the voltage applied to the second anti-ferroelectric liquid crystal cell LC has the value VA equal to the sum of the level of the first sustain voltage VCM1 and the level of the logic low voltage VSL during the second, fourth, and fifth scan times t2, t4, and t5, if anti-ferroelectric liquid crystal cells LC scanned during the second, fourth, and fifth scan times t2, t4, and t5 among anti-ferroelectric liquid crystal cells LC on the second signal electrode line SL2 are turned ON, as shown in FIG. 4. However, the voltage applied to the second anti-ferroelectric liquid crystal cell LC has the value VB equal to a difference between the level of the first sustain voltage VCM1 and the level of the logic high voltage VSH during the third scan time t3, if anti-ferroelectric liquid crystal cells LC scanned during the third scan time t3 among anti-ferroelectric liquid crystal cells LC on the second signal electrode line SL2 are turned OFF, as shown in
During a first scan time t1′ of a second frame, the voltages applied to the respective first and second anti-ferroelectric liquid crystal cells LC which are turned ON has a level VCL+VSH which is the sum of the level of the second scan selection voltage VCL of FIG. 3 and the level of the logic high voltage VSH of the display data signal. During a sustain period ranging from a second scan time t2′ to a fifth scan time t5′, while the second scan selection voltage VCL is applied to the other scan electrode lines CL2 through CL5, the voltage applied to the first anti-ferroelectric liquid crystal cell LC has a level VA equal to the sum of the level of the second sustain voltage VCM2 and the level of the logic high voltage VSH, if the logic high voltage VSH is applied to the first signal electrode line SL1, and has a level VB equal to a difference between the level of the second sustain voltage VCM2 and the level of the logic low voltage VSL, if the logic low voltage VSL is applied to the first signal electrode line SL1. Accordingly, during the sustain period ranging from t2′ to t5′, the voltage applied to the first anti-ferroelectric liquid crystal cell LC is constant at the level VA equal to the sum of the level of the second sustain voltage VCM2 and the level of the logic high voltage VSH, if the logic high voltage VSH is applied to the first signal electrode line SL1, while the second scan selection voltage VCL is applied to the other scan electrode lines CL2 through CL5, as shown in
Meanwhile, during the sustain period ranging from t2′ to t5′ following the first scan time t1′ in the second frame, while the second scan selection voltage VCL is applied to the other scan electrode lines CL2 through CL5, a voltage applied to the second anti-ferroelectric liquid crystal cell LC has a level VA equal to the sum of the level of the second sustain voltage VCM2 and the level of the logic high voltage VSH, if the logic high voltage VSH is applied to the second signal electrode line SL2, and has a level VB equal to a difference between the level of the second sustain voltage VCM2 and the level of the logic low voltage VSL, if the logic low voltage VSL is applied to the second signal electrode line SL2. Accordingly, the voltage applied to the second anti-ferroelectric liquid crystal cell LC has the value VA equal to the sum of the level of the second sustain voltage VCM2 and the level of the logic high voltage VSH during the second, fourth, and fifth scan times t2′, t4′, and t5,′ if anti-ferroelectric liquid crystal cells LC scanned during the second, fourth, and fifth scan times t2′, t4′, and t5′ among anti-ferroelectric liquid crystal cells LC on the second signal electrode line SL2 are turned ON, as shown in FIG. 4. However, the voltage applied to the second anti-ferroelectric liquid crystal cell LC has the value VB equal to a difference between the level of the second sustain voltage VCM2 and the level of the logic low voltage VSL during the third scan time t3,′ if anti-ferroelectric liquid crystal cells LC scanned during the third scan time t3′ among anti-ferroelectric liquid crystal cells LC on the second signal electrode line SL2 are turned OFF, as shown in
In the above-described conventional driving method, the average level of sustain voltages applied to individual selected anti-ferroelectric liquid crystal cells LC changes, which results in different transmittance. Accordingly, the display characteristics are not uniform.
To solve the above-described problems, it is an object of the present invention to provide a method of driving an anti-ferroelectric LCD panel, in which the average level of sustain voltages applied to individual selected anti-ferroelectric liquid crystal cells is constant so that display characteristics can have uniform transmittance.
To achieve the above object of the present invention, there is provided a method of driving an anti-ferroelectric LCD panel in which signal electrode lines are arranged in parallel above anti-ferroelectric liquid crystal cells and at least first and second scan electrode lines are arranged below the anti-ferroelectric liquid crystal cells, perpendicular to the signal electrode lines. The method includes a first driving step and a second driving step, which are repeated. Each of the first and second driving steps includes a scanning step, an inversion step, and an iteration step. In the scanning step, a scan selection voltage is applied to the first scan electrode line, and simultaneously, display data signals are applied to the signal electrode lines. In the inversion step, a sustain voltage is applied to the first scan electrode line, and simultaneously, inverted signals of the display data signals, which have been applied during the scanning step, are applied to the signal electrode lines. In the iteration step, the scanning and inversion steps are repeatedly performed with respect to the second scan electrode line and all of the signal electrode lines.
According to the present invention, during an inversion step, the inverted signals of display data signals are applied to signal electrode lines, so the average level of sustain voltages applied to selected anti-ferroelectric liquid crystal cells is constant. Accordingly, display characteristics of uniform transmittance can be obtained.
Accordingly, since the state of anti-ferroelectric liquid crystal cells selected during the first driving step is inverted at the beginning of the second driving step, the degree of state conversion of the anti-ferroelectric liquid crystal cells increases in the second driving step so that the reliability of selection of the anti-ferroelectric liquid crystal cells can be increased.
The above objects and advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings, in which:
In an anti-ferroelectric LCD panel to which an embodiment of the present invention is applied, signal electrode lines SL1 through SLm of
Referring to
During the scan times (the first halves) of the respective driving periods t1 through tn, a first scan selection voltage VCH is sequentially applied to the scan electrode lines CL1 through CLn to be scanned, and simultaneously first display data signals SS1 through SSn, having voltages VSH1 and VG lower than the first scan selection voltage VCH, are applied to the signal electrode lines SL1 through SLm. Accordingly, when the first scan selection voltage VCH is applied to one scan electrode line and the second scan selection data voltage VG is applied to selected signal electrode lines, selected anti-ferroelectric liquid crystal cells LC (shown in
During the inversion times (the last halves) of the respective driving periods t1 through tn, a first sustain voltage VCM1, which is lower than the first scan selection voltage VCH and higher than the voltages VSH1 and VG of the first display data signals SS1 through SSn, is applied to the scan electrode CL1 through CLn, which have been scanned, and simultaneously, inverted signals of the first display data signals SS1 through SSn applied during the scan times of the respective driving periods t1 through tn are applied to the signal electrode lines SL1 through SLm.
Accordingly, during one scan time, the first sustain voltage VCM1 is continuously applied to a scan electrode line having selected anti-ferroelectric liquid crystal cells LC, and simultaneously, the first display data signals SS1 through SSn and their inverted signals are continuously applied to the signal electrode lines SL1 through SLm. As a result, the positive ferroelectric state is maintained so that the external light can be continuously transmitted through the selected anti-ferroelectric liquid crystal cells LC (refer to the operation corresponding to the D2 direction of FIG. 2). Here, the average level of voltages applied to each of the signal electrode lines SL1 through SLm is equal to half of a difference between the nonselection data voltage VSH1 and the selection data voltage VG, and is constant. Accordingly, the average level of sustain voltages applied to each of the selected anti-ferroelectric liquid crystal cells LC is constant, so display characteristics of uniform transmittance can be obtained.
In a second modulation period (from t1′ through tn′ in the case of the waveform S1) corresponding to a second driving step, each of the driving periods (t1′ through tn′) is divided into a scan time (the first half of each driving period t1′ through tn′) and an inversion time (the last half of each driving period t1′ through tn′).
During the scan times (the first halves) of the respective driving periods t1′ through tn′, a second scan selection voltage VG is sequentially applied to the scan electrode lines CL1 through CLn to be scanned, and simultaneously, second display data signals SS1′ through SSn′ having voltages VCH and VSL2 higher than the second scan selection voltage VG are applied to the signal electrode lines SL1 through SLm. Accordingly, when the second scan selection voltage VG is applied to one scan electrode line and the selection data voltage VCH is applied to selected signal electrode lines, selected anti-ferroelectric liquid crystal cells LC are converted into a negative ferroelectric state. Then, external light starts to be transmitted through the selected anti-ferroelectric liquid crystal cells LC (refer to the operation corresponding to the D3 direction of FIG. 2).
During the inversion times (the last halves) of the respective driving periods t1′ through tn′, a second sustain voltage VCM2, which is higher than the second scan selection voltage VG and lower than the voltages VCH and VSL2 of the second display data signals SS1′ through SSn′, is applied to the scan electrode CL1 through CLn, which have been scanned, and simultaneously, inverted signals of the second display data signals SS1′ through SSn′ applied during the scan times of the respective driving periods t1′ through tn′ are applied to the signal electrode lines SL1′ through SLm′.
Accordingly, during one scan time, the second sustain voltage VCM2 is continuously applied to a scan electrode line having selected anti-ferroelectric liquid crystal cells LC, and simultaneously, the second display data signals SS1′ through SSn′ and their inverted signals are continuously applied to the signal electrode lines SL1 through SLm. As a result, the negative ferroelectric state is maintained so that the external light is continuously transmitted through the selected anti-ferroelectric liquid crystal cells LC (refer to the operation corresponding to the D4 direction of FIG. 2). Here, the average level of voltages applied to each of the signal electrode lines SL1 through SLm is equal to half of a difference between the nonselection data voltage VSL2 and the selection data voltage VCH, and is constant. Accordingly, the average level of sustain voltages applied to each of the selected anti-ferroelectric liquid crystal cells LC is constant, so that uniform transmittance display characteristics can be obtained.
During the first modulation period (from t1 through tn in the case of the waveform S1) corresponding to the first driving step and during the second modulation period (from t1′ through tn′ in the case of the waveform S1) corresponding to the second driving step, the polarities of voltages applied to signal electrode lines and scan electrode lines are constant. The polarity of voltages applied to anti-ferroelectric liquid crystal cells LC during the first modulation period (from t1 through tn in the case of the waveform S1) is opposite to the polarity of voltages applied to anti-ferroelectric liquid crystal cells LC during the second modulation period (from t1′ through tn′ in the case of the waveform S1). Briefly, the scan selection voltage VCH and the selection data voltage VG during the first modulation period (from t1 through tn in the case of the waveform S1) corresponding to the first driving step are inverted during the second modulation period (from t1′ through tn′ in the case of the waveform S1) corresponding to the second driving step. Accordingly, the state of anti-ferroelectric liquid crystal cells LC selected during the first modulation period (from t1 through tn in the case of the waveform S1) is inverted at the beginning of the second modulation period (from t1′ through tn′ in the case of the waveform S1), so the degree of state conversion of the anti-ferroelectric liquid crystal cells LC increases in the second modulation period (from t1′ through tn′ in the case of the waveform S1) so that the reliability of selection of the anti-ferroelectric liquid crystal cells LC increases.
Referring to
Meanwhile, during the first inversion time (the last half of t1) in the first modulation period (from t1 through tn in the case of the waveform S1) corresponding to the first driving step, due to the inversion of a signal voltage applied to the second signal electrode line SL2, the voltage applied to the second anti-ferroelectric liquid crystal cell LC has a level VB. In this case, VB is equal to a difference between the level of the first sustain voltage VCM1 and the level of the logic high voltage VSL (see the waveform VW2). In the following sustain period ranging from t2 to t5, in the case where anti-ferroelectric liquid crystal cells LC scanned during the second, fourth, and fifth scan times (the first halves of t2, t4, and t5) among anti-ferroelectric liquid crystal cells LC on the second signal electrode line SL2 are turned ON, the voltage applied to the second anti-ferroelectric liquid crystal cell LC has the value VA. In this case, VA is equal to the difference between the level of the first sustain voltage VCM1 and the level of the logic low voltage VG during the second, fourth, and fifth scan times (the first halves of t2, t4, and t5) for the second, fourth, and fifth scan electrode lines CL2, CL4, and CL5, and has the level VB equal to the difference between the level of the first sustain voltage VCM1 and the level of the logic high voltage VSH1 during the second, fourth, and fifth inversion times (the last halves of t2, t4, and t5) for the second, fourth, and fifth scan electrode lines CL2, CL4, and CL5. In the case where an anti-ferroelectric liquid crystal cell LC scanned during the third scan time (the first half of t3) among anti-ferroelectric liquid crystal cells LC on the second signal electrode line SL2 is turned OFF, the voltage applied to the second anti-ferroelectric liquid crystal cell LC has the value VB equal to the difference between the level of the first sustain voltage VCM1 and the level of the logic high voltage VSH1 during the third scan time (the first half of t3) for the third scan electrode line CL3, and has the value VA equal to the difference between the level of the first sustain voltage VCM1 and the level of the logic low voltage VG during the third inversion time (the last half of t3) for the third scan electrode line CL3. During the sustain period ranging from t2 to t5, the average level of the voltage applied to the second anti-ferroelectric liquid crystal cell LC is (VA+VB)/2 and is the same as that applied to the first anti-ferroelectric liquid crystal cell LC.
A voltage applied to the first and second anti-ferroelectric liquid crystal cells LC, which are turned ON during a first scan time (the first half of t1′) in the second modulation period (from t1′ through tn′ in the case of the waveform S1) corresponding to the second driving step, has a level VCH−VG equal to a difference between the level of the second scan selection voltage VG of FIG. 5 and the level of the logic high voltage VCH of
Meanwhile, during the first inversion time (the last half of t1′) in the second modulation period (from t1′ through tn′ in the case of the waveform S1) corresponding to the second driving step, due to the inversion of a signal voltage applied to the second signal electrode line SL2, the voltage applied to the second anti-ferroelectric liquid crystal cell LC has a level VB equal to a difference between the level of the second sustain voltage VCM2 and the level of the logic low voltage VSL2 (see the waveform VW2). In the following sustain period ranging from t2′ to t5′, in the case where anti-ferroelectric liquid crystal cells LC scanned during the second, fourth, and fifth scan times (the first halves of t2′, t4′, and t5′) among anti-ferroelectric liquid crystal cells LC on the second signal electrode line SL2 are turned ON, the voltage applied to the second anti-ferroelectric liquid crystal cell LC has the value VA equal to the difference between the level of the second sustain voltage VCM2 and the level of the logic high voltage VCH during the second, fourth, and fifth scan times (the first halves of t2′, t4′, and t5′) for the second, fourth, and fifth scan electrode lines CL2, CL4, and CL5, and has the level VB equal to the difference between the level of the second sustain voltage VCM2 and the level of the logic low voltage VSL2 during the second, fourth, and fifth inversion times (the last halves of t2′, t4′, and t5′) for the second, fourth, and fifth scan electrode lines CL2, CL4, and CL5. In the case where an anti-ferroelectric liquid crystal cell LC scanned during the third scan time (the first half of t3′) among anti-ferroelectric liquid crystal cells LC on the second signal electrode line SL2 is turned OFF, the voltage applied to the second anti-ferroelectric liquid crystal cell LC has the value VB equal to the difference between the level of the second sustain voltage VCM2 and the level of the logic low voltage VSL2 during the third scan time (the first half of t3′) for the third scan electrode line CL3, and has the value VA equal to the difference between the level of the second sustain voltage VCM2 and the level of the logic high voltage VCH during the third inversion time (the last half of t3′) for the third scan electrode line CL3. During the sustain period ranging from t2′ to t5′, the average level of the voltage applied to the second anti-ferroelectric liquid crystal cell LC is (VA+VB)/2 and is the same as that applied to the first anti-ferroelectric liquid crystal cell LC.
As described above, in a method for driving an anti-ferroelectric LCD panel according to an embodiment of the present invention, during an inversion step, the inverted signals of display data signals are applied to signal electrode lines, so the average level of sustain voltages applied to selected anti-ferroelectric liquid crystal cells is constant. Accordingly, uniform transmittance display characteristics can be obtained.
The present invention is not restricted to the above-described embodiments, but the embodiments can be modified and changed by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Number | Date | Country | Kind |
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2001-60976 | Sep 2001 | KR | national |
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Number | Date | Country | |
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20030063060 A1 | Apr 2003 | US |