Patent Application
20110249033
This application claims priority to Korean Patent Application No. 2010-33881, filed on Apr. 13, 2010, the disclosure of which is incorporated by reference in its entirety herein.
1. Technical Field
Embodiments of the present invention relate to a method of driving a backlight assembly capable of improving display quality and reducing power consumption, and a display apparatus having the backlight assembly.
2. Discussion of Related Art
A liquid crystal display (LCD) is thin, light weight, and uses a small amount of power. Therefore, the LCD is often developed for monitors of notebook computers, desktop computers, cell phones, and TVs. The LCD includes a liquid crystal display panel that controls light transmittance of liquid crystal and a light source disposed below the liquid crystal display to provide the light to the liquid crystal. Unlike a cathode ray tube (CRT), which employs an impulsive driving method having a fast response speed, the LCD is a hold type display device that continuously displays one image during one frame period, with a slow response speed. Thus, the LCD provides a clear image when displaying a still image. However, when displaying a moving picture, the slow response speed of the liquid crystal causes after images or motion blurring on the liquid crystal display panel.
At least one exemplary embodiment of the present invention provides a method of driving a backlight assembly employing a scanning method and a dimming method to drive a light source.
At least one exemplary embodiment of the present invention provides a display apparatus having the backlight assembly.
According to an exemplary embodiment of the present invention, a backlight assembly includes a plurality of light emitting blocks, a scan signal generator sequentially outputting at least two scan signals having a scanning frequency synchronized with a frame frequency of a display, a dimming step selector selecting a dimming step for each of the light emitting blocks among a plurality of dimming steps in response to local dimming data generated based on an image signal input to the display, a clock generator converting a predetermined reference clock to a dimming clock having a dimming frequency corresponding to multiplying the scanning frequency by the number of dimming steps and then dividing by a duty ratio of each scan signal, and a dimming signal generator counting the dimming step of each of the light emitting blocks using the dimming clock to generate dimming signals based on the counted values and the scan signals.
According to an exemplary embodiment of the invention, a method of driving a backlight assembly having a brightness corresponding to one of a plurality of dimming steps to provide light to a display panel, where the backlight assembly includes at least two light emitting blocks having at least one sub-block includes sequentially outputting at least two scan signals having a scanning frequency synchronized with a frame frequency of the display panel, determining a dimming step of each of the light emitting blocks in response to a local dimming data generated based on an image signal provided to the display panel, converting a predetermined reference clock to a dimming clock having a frequency corresponding to the scanning frequency multiplied by the number of dimming steps and then divided by a duty ratio of each of the scan signals, and counting the dimming step of each of the light emitting blocks using the dimming clock and combining the counted values with the scan signals to generate dimming signals each having a dimming duty ratio corresponding to the dimming step of each of the light emitting blocks.
According to an exemplary embodiment of the invention, a display apparatus includes a backlight assembly and a display panel. The backlight assembly generates a light. The display panel receives the light to display an image corresponding to an image signal. The backlight assembly includes a backlight unit having a plurality of light emitting blocks that sequentially generate a light in synchronization with a frame frequency of the display panel and a backlight control unit controlling an operation of the backlight unit.
The backlight control unit includes a scan signal generator, a dimming step selector, a clock generator, and a dimming signal generator. The scan signal generator sequentially outputs at least two scan signals having a scanning frequency synchronized with the frame frequency, and the dimming step selector selects a dimming step of each of the light emitting blocks among a plurality of dimming steps in response to a local dimming data generated based on the image signal provided to the display panel. The clock generator converts a predetermined reference clock to a dimming clock having a dimming frequency corresponding to multiplying the scanning frequency by the number of dimming steps and then dividing by the duty ratio of each scan signal. The dimming signal generator counts the dimming step of each of the light emitting blocks using the dimming clock and combines the counted values with the scan signals, so that dimming signals having a dimming duty ratio corresponding to the dimming steps of the light emitting blocks are generated.
According to at least one embodiment of the invention, when the frequency of the dimming clock used to count the dimming step according to the duty ratio of each of the scan signals is changed, a scanning method and a dimming method may be simultaneously applied to the backlight assembly to drive the backlight assembly without a distortion of the local dimming data. Thus, power consumption of the display apparatus may be reduced and display quality of the display apparatus may be improved.
Embodiments of the present invention will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:
It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. Like numbers refer to like elements throughout. Hereinafter, exemplary embodiments of the present invention will be explained in detail with reference to the accompanying drawings.
The liquid crystal display panel 210 includes a plurality of gate lines GL1˜GLn, a plurality of data lines DL1˜DLm crossing the gate lines GL1˜GLn, and pixels arranged in the liquid crystal display panel 210. For the convenience of explanation, one pixel has been shown in
The timing controller 220 receives an image signal RGB, a horizontal synchronization signal H_sync, a vertical synchronization signal V_sync, a clock signal MCLK, and a data enable signal DE from an external device. The timing controller 220 converts a data format of the image signal RGB to a data format appropriate to interface between the timing controller 220 and the data driver 240 and outputs the converted image signal R′G′B′ to the data driver 240. Further, the timing controller 220 outputs data control signals, such as an output start signal TP, a horizontal start signal STH, and a clock signal HCLK to the data driver 240 and outputs gate control signals, such as a vertical start signal STV, a gate clock signal CPV, and an output enable signal OE, to the gate driver 230.
The gate driver 230 sequentially applies gate signals G1˜Gn to the gate lines GL1˜GLn of the liquid crystal display panel 210 in response to the gate control signals STV, CPV and OE provided from the timing controller 220 to sequentially scan the gate lines GL1˜GLn.
The data driver 240 generates a plurality of grey-scale voltages using gamma voltages provided from a gamma voltage generator (not shown). The data driver 240 selects grey-scale voltages corresponding to the image signal R′G′B′ among the generated grey-scale voltages in response to the data control signals TP, STH and HCLK provided from the timing controller 220 and applies the selected grey-scale voltages to the data lines DL1˜DLm of the liquid crystal display panel 210 as data signals D1˜Dm.
When the gate signals G1˜Gn are sequentially applied to the gate lines GL1˜GLn, the data signals D1˜Dm are applied to the data lines DL1˜DLm in synchronization with the gate signals G1˜Gn. When a selected gate line receives a corresponding gate signal, a thin film transistor Tr connected to the selected gate line is turned on in response to the corresponding gate signal. When a data signal is applied to a data line connected to the turned-on thin film transistor Tr, the applied data signal is charged to the liquid crystal capacitor CLC and the storage capacitor CST through the turned-on thin film transistor Tr.
The liquid crystal capacitor CLC controls a light transmittance of a liquid crystal according to the charged voltage therein. The storage capacitor CST stores the data signal when the thin film transistor Tr1 is turned on and applies the stored data signal to the liquid crystal capacitor CLC when the thin film transistor Tr1 is turned off to maintain the liquid crystal capacitor CLC in the charged state. The liquid crystal display panel 210 may display the image through the above stated method.
The backlight assembly 100 includes a backlight unit 110 arranged at a rear of the liquid crystal display panel 210 to provide a light to the liquid crystal display panel 210, a voltage converting circuit 130 providing a driving voltage VLED to the backlight unit 110, and a backlight control unit 120 controlling an on/off operation of the backlight unit 110.
Referring to
The backlight unit 110 includes N (N is a natural number larger than 1) light emitting blocks (e.g., ch1˜ch8) arranged in a first direction D1. In at least one exemplary embodiment, the backlight unit 110 may include eight light emitting blocks ch1˜ch8 (hereinafter, referred to as first to eighth light emitting blocks). In addition, each of the light emitting blocks ch1˜ch8 may be divided into J (J is a natural number larger than 1) sub-blocks (e.g., b1˜b8) arranged in a second direction D2 that is substantially perpendicular to the first direction D1. In at least one exemplary embodiment, each of the light emitting blocks ch1˜ch8 includes eight sub-blocks b1˜b8. Thus, sixty-four sub-blocks b1˜b64 may be arranged in the backlight unit 110 in total. However, in alternate embodiments, the backlight unit 110 may include a lesser or greater number of light emitting blocks and each light emitting block may include a lesser or greater number of sub-blocks.
The first to eighth sub-blocks b1˜b8 have been shown in
The voltage converting circuit 130 includes a direct current-to-direct current (DC/DC) converter 133 converting an input voltage Vin, for example, of about 12V to output the driving voltage VLED and a control circuit 135 controlling the DC/DC converter 133.
The DC/DC converter 133 may include a coil (inductor) L1, a diode Di1, a capacitor C1, and a transistor T1 (hereinafter, referred to as switching device). The transistor T1 includes a control terminal (gate) connected to the control circuit 135 to receive a switching signal SW1.
The switching device T1 is turned on or turned off in response to the switching signal SW1, and the coil L1 boosts up the input voltage Vin according to the on/off operation of the switching device T1. Thus, a voltage level of the driving voltage VLED output from the DC/DC converter 133 may vary according to a duty ratio of the switching signal SW1.
For example, when the duty ratio of the switching signal SW1 decreases, the voltage level of the driving voltage VLED output from the DC/DC converter 133 decreases. Alternately, the voltage level of the driving voltage VLED increases as the duty ratio of the switching signal SW1 increases. In at least one exemplary embodiment of the invention, the driving voltage VLED may have voltage level of about 20V to about 35V.
The backlight control unit 120 is connected to an output terminal of each of the first to eighth sub-blocks b1˜b8 to apply a control signal CS to the control circuit 135 to control the duty ratio of the switching signal SW1 based on a current value feedback from each of the first to eighth sub-blocks b1˜b8.
Further, the backlight control unit 120 receives the vertical synchronization signal V_sync and a local dimming data LDD from an external source to control brightness of each of the first to eighth sub-blocks b1˜b8.
The scan synchronization signal generator 121 receives the vertical synchronization signal V_sync. The vertical synchronization signal V_sync is used to determine a frame period of the liquid crystal display panel 210. Hereinafter, a frequency of the vertical synchronization signal V_sync is referred to as a frame frequency 1 FHz. The frame frequency 1 FHz may be set to, for example, about 60 Hz, 120 Hz, 240 Hz, etc.
The scan synchronization signal generator 121 outputs a scan synchronization signal Scan_sync to control a scan timing of each of the light emitting blocks ch1˜ch8 based on the vertical synchronization signal V_sync. A frequency of the scan synchronization signal Scan_sync depends upon the number of the light emitting blocks ch1˜ch8. As shown in
The scan signal generator 122 generates first to eighth scan signals Scan1˜Scan8 based on the scan synchronization signal Scan_sync, and the first to eighth scan signals Scan1˜Scan8 are sequentially applied to the first to eighth light emitting blocks ch1˜ch8.
The dimming step selector 124 selects a dimming step of each of the sub-blocks b1˜b64 among predetermined P (for example, P may be 2k, where P and k are larger than 1) dimming steps Step 1˜Step 2k based on the local dimming data LDD. The local dimming data LDD is calculated based on the image signal R′G′B′ applied to a predetermined dimming area of the liquid crystal display panel 210 corresponding to the sub-blocks b1˜b64. As an example, the local dimming data LDD may be an average grey-scale value of the image signal R′G′B′ applied to each of the dimming areas.
For example, when the dimming step is presented as an 8-bit signal (i.e., the k is 8), the dimming step selector 124 may receive 256 dimming steps (i.e., the P is 256). In another example, where the dimming step is presented as a 10-bit signal (i.e., the k is 10), the dimming step selector 124 may receive 1024 dimming steps (i.e., the P is 1024).
The dimming step selector 124 selects a dimming step corresponding to the local dimming data LDD as a dimming step of a corresponding sub-block. The selected dimming steps S1˜S64 of the sub-blocks b1˜b64 are applied to the dimming signal generator 125.
The clock generator 123 receives a reference clock REF_clk having a predetermined frequency and converts the reference clock REF_clk to a dimming clock DIM_clk based on the duty ratio of each of the scan signals Scan1˜Scan8 and the number of the dimming steps (that is, the P). For example, the dimming clock DIM_clk has a dimming frequency corresponding to a value obtained by dividing a value obtained by multiplying the frame frequency 1 FHz and the P by the duty ratio SDD of each of the scan signals Scan1˜Scan8.
The dimming signal generator 125 counts the dimming steps S1˜S64 corresponding to each of the sub-blocks b1˜b64 using the dimming clock DIM_clk. Further, the dimming signal generator 125 receives the first to eighth scan signals Scan1˜Scan8 and applies the counted values to each of the first to eighth scan signals Scan1˜Scan8 to output first to sixty-fourth dimming signals DIM1˜DIM64 to be applied to the sub-blocks b1˜b64.
Hereinafter, an operation of the backlight control unit 120 shown in
The scan synchronization signal Scan_sync has the frequency (1 F×8 Hz) corresponding to eight times the frame frequency 1 FHz to control the scan timing of each of the light emitting blocks ch1˜ch8.
The scan signal generator 122 generates the first to eighth scan signals Scan1˜Scan8 based on the scan synchronization signal Scan_sync to sequentially apply the first to eighth scan signals Scan1˜Scan8 to the first to eighth light emitting blocks ch1˜ch8. As shown in
In addition, each of the first to eighth scan signals Scan1˜Scan8 has a duty ratio larger than 0 and smaller than 1. As an example of at least one exemplary embodiment, each of the first to eighth scan signals Scan1˜Scan8 may have a higher period corresponding to ⅜ths of the one frame period 1 F. Therefore, the higher periods of the two scan signals adjacent each other among the first to eighth scan signals Scan1˜Scan8 may partially overlap with each other.
Through the above-stated procedure, the first to eighth light emitting blocks ch1˜ch8 are shifted one by one from the first timing t1 during one frame period 1 F, and thus the first to eighth light emitting blocks ch1˜ch8 may be sequentially turned on.
Referring to
As shown in
Referring to
When this occurs, the dimming signal generator 125 counts the dimming steps of each of the sub-blocks b1˜b64 using the dimming clock DIM_clk to generate dimming signals DIM1˜DIM64 respectively corresponding to the sub-blocks b1˜b64.
As shown in
When the ninth sub-block b9 has 115 dimming steps, the dimming signal generator 125 counts the dimming clock DIM_clk from the start timing of the one frame period 1 F and generates a ninth dimming signal DIM9 having a high period until the counted value of the dimming clock DIM_clk reaches 115.
Similarly, seventeenth, twenty-fifth, thirty-third, forty-first, forty-ninth, and fifty-seventh dimming signals DIM17, DIM25, DIM33, DIM 41, DIM49, and DIM 57 corresponding to the seventeenth, twenty-fifth, thirty-third, forty-first, forty-ninth, and fifty-seventh sub-blocks b17, b25, b33, b41, b49, and b57 may be generated.
The dimming signal generator 125 counts the dimming steps of each of the sub-blocks b1˜b64 using the dimming clock DIM_clk to generate dimming signals DIM1˜DIM64 respectively corresponding to the sub-blocks b1˜b64.
As shown in
When the ninth sub-block b9 has 115 dimming steps, the dimming signal generator 125 sets a period from a rising timing a2 of the second scan signal Scan2 to a time point at which the 115 dimming clocks DIM_clk are generated to the high period of the ninth dimming signal DIM9.
Similarly, the dimming signal generator 125 may set the high period of the seventeenth, twenty-fifth, thirty-third, forty-first, forty-ninth, and fifty-seventh dimming signals DIM17, DIM25, DIM33, DIM 41, DIM49, and DIM 57 respectively applied to the seventeenth, twenty-fifth, thirty-third, forty-first, forty-ninth, and fifty-seventh sub-blocks b17, b25, b33, b41, b49, and b57.
As described above, when the frequency of the dimming clock DIM_clk used to count the dimming steps is changed according to the duty ratio of each of the scan signals Scan1˜Scan8, a scanning method and a dimming method may be simultaneously applied to the backlight assembly 100 without a distortion of the local dimming data LDD.
Referring to
Referring to
As shown in
The scan signal generator 142 generates first to eighth scan signals Scan1˜Scan8 based on the scan synchronization signal Scan_sync and sequentially applies the first to eighth scan signals Scan1˜Scan8 to the first to eighth light emitting blocks ch1˜ch8. Thus, a duty ratio of the first to eighth scan signals Scan1˜Scan8 depends upon the duty ratio of the global dimming signal GDD. When the global dimming signal GDD has a duty ratio of about 50%, each of the first to eighth scan signals Scan1˜Scan8 has a duty ratio corresponding to a value obtained by dividing a value obtained by multiplying one frame period 1 F and the duty ratio of the global dimming signal GDD (1 F×50%) by ⅜.
The clock generator 143 receives a reference clock REF_clk having a predetermined frequency and converts the reference clock REF_clk to a dimming clock GDIM_clk based on the duty ratio of each of the scan signals Scan1˜Scan8 and the number of the dimming steps (e.g., P steps).
For example, the dimming clock GDIM_clk has a dimming frequency corresponding to a value obtained by dividing a value obtained by multiplying the frame frequency 1 FHz and the P by the duty ratio SDD of each of the scan signals Scan1˜Scan8.
When the number of the dimming steps is about 256 and each of the scan signals Scan1˜Scan8 has the duty ratio (1 F×( 3/16)) corresponding to a value obtained by dividing a value obtained by multiplying one frame period 1 F and the duty ratio (50%) by ⅜, the dimming clock GDIM_clk has the dimming frequency ((1 F×256)/( 3/16)) corresponding to a value obtained by dividing a value obtained by multiplying the frame frequency 1 FHz and 256 by the duty ratio (1 F×( 3/16)) of each of the scan signals Scan1˜Scan8. Consequently, the dimming clock GDIM_clk may have 256 high periods during a high period of each of the scan signals Scan1˜Scan8.
The dimming signal generator 145 counts the dimming steps of each sub-block b1˜b64 using the dimming clock GDIM_clk to generate dimming signals GDIM1˜GDIM64 corresponding to the sub-blocks b1˜b64, respectively.
As shown in
When the ninth sub-block b9 has 115 dimming steps, the dimming signal generator 145 sets a period from a rising timing a2 of a second scan signal Scan2 to a time point at which 115 dimming clocks GDIM_clk are generated to a high period of a ninth dimming signal GDIM9.
Similarly, the dimming signal generator 145 may set the high period of seventeenth, twenty-fifth, thirty-third, forty-first, forty-ninth, and fifty-seventh dimming signals GDIM17, GDIM25, GDIM33, GDIM 41, GDIM49, and GDIM 57 respectively applied to seventeenth, twenty-fifth, thirty-third, forty-first, forty-ninth, and fifty-seventh sub-blocks b17, b25, b33, b41, b49, and b57.
According to at least one embodiment of the invention, when the frequency of the dimming clock GDIM_clk used to count the dimming steps is changed according to the duty ratio of each of the scan signals Scan1˜Scan8, the scanning method and the dimming method may be simultaneously applied to the backlight assembly 100 without the distortion of the local dimming data LDD.
Although exemplary embodiments of the present invention have been described, it is to be understood that the present invention is not limited to these exemplary embodiments and various changes and modifications can be made by one ordinary skilled in the art within the spirit and scope of the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2010-0033881 | Apr 2010 | KR | national |
