Patent Grant
8698851
This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2010-0073930, filed on Jul. 30, 2010, the disclosure of which is incorporated by reference herein in its entirety.
1. Technical Field
Exemplary embodiments of the present invention relate to a method of driving a display panel and a display apparatus for performing the method. More particularly, exemplary embodiments of the present invention relate to a method of driving a display panel for improving display quality and a display apparatus for performing the method.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) apparatus includes an LCD panel, a data driver, and a gate driver. The LCD panel may include an array substrate, a color filter substrate, and a liquid crystal layer. The array substrate may include a plurality of data lines, a plurality of gate lines, a plurality of switching elements, and a plurality of pixel electrodes. For example, the array substrate may include I×J switching elements electrically connected to I data lines and J gate lines, and I×J pixel electrodes electrically connected to the switching elements. I and J are natural numbers. The color filter substrate may include a plurality of color filters and a common electrode. The LCD panel is driven by way of the data driver providing data voltages to the I data lines, and the gate driver providing gate signals to the J gate lines.
Increasing the frame rate of the LCD panel when driving the LCD panel may improve image distortion such as, for example, a motion blur effect. However, as a result of the high frame rate, the time required to charge a data voltage to a pixel is relatively decreased. Similarly, the time required to recover from distortion of the data voltage applied to the pixel electrode, and distortion of a common voltage applied to the common electrode is decreased. This results in image distortion such as, for example, a greenish effect occurring when a vertical stripe pattern is displayed on the LCD panel, non-uniform luminance distribution, or cross talk.
Exemplary embodiments of the present invention provide a method of driving a display panel capable of preventing image distortion.
Exemplary embodiments of the present invention also provide a display apparatus for performing the above-mentioned method.
According to an exemplary embodiment of the present invention, a display apparatus includes a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, a sixth pixel, a seventh pixel and an eighth pixel. The first pixel includes a first pixel electrode electrically connected to the first data line and a first gate line through a first switching element. The second pixel includes a second pixel electrode electrically connected to the second data line and a second gate line through a second switching element. The third pixel includes a third pixel electrode electrically connected to the third data line and the first gate line through a third switching element. The second and third data lines are adjacent to each other and disposed between the first and third pixels. The fourth pixel includes a fourth pixel electrode electrically connected to the fourth data line and the second gate line through a fourth switching element. The fifth pixel includes a fifth pixel electrode electrically connected to the fifth data line and the second gate line through a fifth switching element. The fourth and fifth data lines are adjacent to each other and disposed between the fourth and fifth pixels The sixth pixel includes a sixth pixel electrode electrically connected to the sixth data line and the first gate line through a sixth switching element. The seventh pixel includes a seventh pixel electrode electrically connected to the seventh data line and the second gate line through a seventh switching element. The sixth and seventh data lines are adjacent to each other and disposed between the fifth and seventh pixels. The eighth pixel includes an eighth pixel electrode electrically connected to the eighth data line and the first gate line through an eighth switching element.
According to an exemplary embodiment of the present invention, a method of driving a display panel includes applying data voltages to a first, second, third, fourth, fifth, sixth, seventh, and eighth data line of the display panel, and applying the same gate signal to first and second gate lines of the display panel. The display panel includes a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, a sixth pixel, a seventh pixel and an eighth pixel. The first pixel includes a first pixel electrode electrically connected to the first data line and a first gate line through a first switching element. The second pixel includes a second pixel electrode electrically connected to the second data line and a second gate line through a second switching element. The third pixel includes a third pixel electrode electrically connected to the third data line and the first gate line through a third switching element. The second and third data lines are adjacent to each other and disposed between the first and third pixels. The fourth pixel includes a fourth pixel electrode electrically connected to the fourth data line and the second gate line through a fourth switching element. The fifth pixel includes a fifth pixel electrode electrically connected to the fifth data line and the second gate line through a fifth switching element. The fourth and fifth data lines are adjacent to each other and disposed between the fourth and fifth pixels The sixth pixel includes a sixth pixel electrode electrically connected to the sixth data line and the first gate line through a sixth switching element. The seventh pixel includes a seventh pixel electrode electrically connected to the seventh data line and the second gate line through a seventh switching element. The sixth and seventh data lines are adjacent to each other and disposed between the fifth and seventh pixels. The eighth pixel includes an eighth pixel electrode electrically connected to the eighth data line and the first gate line through an eighth switching element.
According to an exemplary embodiment of the present invention, a method of driving a display panel includes applying a gate signal to first and second adjacent pixel rows simultaneously, applying two voltages having opposite polarities to two adjacent data lines, and inverting the polarities of the two applied voltages during consecutive frames. A first pixel in the first adjacent pixel row and a first pixel in the second adjacent pixel row are charged with data voltages having opposite polarities, and a second pixel in the first adjacent pixel row and a second pixel in the second adjacent pixel row are charged with data voltages having opposite polarities. The two adjacent data lines are disposed between two adjacent pixels.
According to an exemplary embodiment of pixel structures of the present invention, distortion of a common voltage may be decreased during polarity inversion driving, resulting in the uniform distribution of luminance and reduced cross talk.
The above and other features of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:
The present invention is described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the present invention are shown. The present invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Like reference numerals refer to like elements throughout the accompanying drawings.
Referring to
The display panel 300 includes a first substrate 100, a second substrate 200 opposing the first substrate 100, and a liquid crystal layer disposed between the first and second substrates 100 and 200.
The first substrate 100 includes a display area and a peripheral area surrounding the display area. A plurality of data lines, a plurality of gate lines crossing the data lines, and a plurality of pixel electrodes are disposed in the display area. The data lines DL1 and DL2 are extended in a first direction D1 and arranged in a second direction D2 crossing the first direction D1. The gate lines GL1 and GL2 are extended in the second direction D2 and arranged in the first direction D1. The pixel electrodes are disposed in a plurality of pixel areas defined on the first substrate 100. For example, the pixel areas may be arranged in a matrix form. A plurality of color filters may be disposed in the pixel areas.
The data driver 500 and a gate driver 150 are disposed in the peripheral area of the first substrate 100. The data driver 500 is disposed in a portion of the peripheral area corresponding to end portions of the data lines DL1 and DL2, and the gate driver 150 is disposed in a portion of the peripheral area corresponding to end portions of the gate lines GL1 and GL2. The gate driver 150 may include a thin film transistor (hereinafter referred to as a “switching element”) disposed in the display area, or a plurality of switching elements disposed in the display area. The gate driver 150 may be directly mounted in the peripheral area of the first substrate 100. Alternatively, the gate driver 150 may be formed as a flexible printed circuit board (not shown) on which a gate driving chip (not shown) is mounted. Similarly, the data driver 500 may be directly mounted in the peripheral area of the first substrate, or formed as a flexible printed circuit board 510 on which a data driving chip 511 is mounted.
The second substrate 200 opposes the first substrate 100. The second substrate 200 includes a common electrode facing the pixel electrodes disposed on the first substrate 100. The second substrate 200 may further include a plurality of color filters.
The display panel 300 may include a plurality of pixels defined by the first substrate 100, the second substrate 200, and the liquid crystal layer. The pixels are disposed in a matrix form having a plurality of pixel rows and a plurality of pixel columns. The pixels may include red, green, and blue pixels. The pixels may be defined using unit pixels including red, green, and blue pixels. For example, when a resolution of the display panel 300 is m×n, the number of the pixels may be m×n×3, the number of data lines may be m×3×2, and the number of gate lines may be n. m and n are natural numbers. In an exemplary embodiment, the display panel may further include a unit pixel including at least one of yellow, cyan, magenta, or white pixels in addition to the red, green, and blue pixels.
For example, a first pixel P1 includes a first switching element T1 electrically connected to a first data line DL1 and a first gate line GL1, and a first liquid crystal capacitor CLC1 electrically connected to the first switching element T1. The first liquid crystal capacitor CLC1 is defined by a first pixel electrode disposed on the first substrate 100, a common electrode disposed on the second substrate 200, and the liquid crystal layer. A common voltage Vcom is provided to the common electrode, and a data voltage having a first polarity with respect to the common voltage Vcom is provided to the first pixel electrode through the first data line DL1. The second pixel P2 is disposed adjacent to the first pixel P1 in the first direction D1. The second pixel P2 includes a second switching element T2 electrically connected to a second data line DL2 and a second gate line GL2, and a second liquid crystal capacitor CLC2 electrically connected to the second switching element T2. The second liquid crystal capacitor CLC2 is defined by a second pixel electrode disposed on the first substrate 100, the common electrode disposed on the second substrate 200, and the liquid crystal layer. The common voltage Vcom is provided to the common electrode, and a data voltage having a second polarity with respect to the common voltage Vcom is provided to the second pixel electrode through the second data line DL2.
The timing controller 400 controls operations of the gate driver 150 and the data driver 500.
The gate driver 150 generates gate signals corresponding to half of the number of the gate lines (e.g., n/2), and sequentially outputs the gate signals in response to the timing controller 400. For example, the gate driver 150 generates a first gate signal, and provides the first gate signal to the first gate line GL1 and the second gate line GL2, which may be electrically connected to each other. Alternatively, when the first gate line GL1 and the second gate line GL2 are not connected to each other, the gate driver 150 may separately provide the first gate signal to the first gate line GL1 and the second gate line GL2 simultaneously.
The data driver 500 provides data signals to the pixels disposed in two pixel rows during a horizontal cycle 1H, in response to the timing controller 400. The data driver 500 provides data signals having opposite polarities to adjacent data lines. For example, the data driver 500 provides a first data signal having a first polarity with respect to the common voltage Vcom to the first data line DL1, and a second data signal having a second, opposite polarity to the second data line DL2. The data driver 500 may invert the polarities of the data signals in every frame when providing the data signals to the data lines.
Referring to
A first pixel P1 includes a first switching element T1 electrically connected to a first data line DL1 and a first gate line GL1, and a first pixel electrode PE1 electrically connected to the first switching element T1. A data signal having a first polarity (+) with respect to a common voltage Vcom is applied to the first data line DL1 at a K-th frame. K is a natural number. A first liquid crystal capacitor of the first pixel P1 may be defined by the first pixel electrode PE1, a common electrode (not shown) opposite the first pixel electrode PE1, and a liquid crystal layer disposed between the first pixel electrode PE1 and the common electrode.
A second pixel P2 is disposed adjacent to the first pixel P1 in the first direction D1. The second pixel P2 includes a second switching element T2 electrically connected to a second data line DL2 and a second gate line GL2, and a second pixel electrode PE2 electrically connected to the second switching element T2. The second gate line GL2 is electrically connected to the first gate line GL1. A data signal having a second polarity (−) with respect to the common voltage Vcom is applied to the second data line DL2 at the K-th frame. The second pixel P2 may include a second liquid crystal capacitor.
A third pixel P3 is disposed adjacent to the first pixel P1 in the second direction D2. The third pixel P3 includes a third switching element T3 electrically connected to a third data line DL3 adjacent to the second data line DL2 and connected to the first gate line GL1, and a third pixel electrode PE3 electrically connected to the third switching element T3. A data signal having the first polarity (+) with respect to the common voltage Vcom is applied to the third data line DL3 at the K-th frame. The third pixel P3 may include a third liquid crystal capacitor.
A fourth pixel P4 is disposed adjacent to the third pixel P3 in the first direction D1. The fourth pixel P4 includes a fourth switching element T4 electrically connected to a fourth data line DL4 and the second gate line GL2, and a fourth pixel electrode PE4 electrically connected to the fourth switching element T4. A data signal having the second polarity (−) with respect to the common voltage Vcom is applied to the fourth data line DL4 at the K-th frame. The fourth pixel P4 may include a fourth liquid crystal capacitor.
A fifth pixel P5 is disposed adjacent to the fourth pixel P4 in the second direction D2. The fifth pixel P5 includes a fifth switching element T5 electrically connected to a fifth data line DL5 adjacent to the fourth data line DL4 and connected to the second gate line GL2, and a fifth pixel electrode PE5 electrically connected to the fifth switching element T5. A data signal having the first polarity (+) with respect to the common voltage Vcom is applied to the fifth data line DL5 at the K-th frame. The fifth pixel P5 may include a fifth liquid crystal capacitor.
A sixth pixel P6 is disposed adjacent to the third pixel P3 in the second direction D2. The sixth pixel P6 includes a sixth switching element T6 electrically connected to a sixth data line DL6 and the first gate line GL1, and a sixth pixel electrode PE6 electrically connected to the sixth switching element T6. A data signal having the second polarity (−) with respect to the common voltage Vcom is applied to the sixth data line DL6 at the K-th frame. The sixth pixel P6 may include a sixth liquid crystal capacitor.
A seventh pixel P7 is disposed adjacent to the fifth pixel P5 in the second direction D2. The seventh pixel P7 includes a seventh switching element T7 electrically connected to a seventh data line DL7 and the second gate line GL2, and a seventh pixel electrode PE7 electrically connected to the seventh switching element T7. A data signal having the first polarity (+) with respect to the common voltage Vcom is applied to the seventh data line DL7 at the K-th frame. The seventh pixel P7 may include a seventh liquid crystal capacitor.
An eighth pixel P8 is disposed adjacent to the sixth pixel P6 in the second direction D2. The eighth pixel P8 includes an eighth switching element T8 electrically connected to an eighth data line DL8 and the first gate line GL1, and an eighth pixel electrode PE8 electrically connected to the eighth switching element T8. A data signal having the second polarity (−) with respect to the common voltage Vcom is applied to the eighth data line DL8 at the K-th frame. The eighth pixel P8 may include an eighth liquid crystal capacitor.
Ninth to sixteenth pixels P9, P10, P11, . . . , P16 are repeatedly disposed in a substantially similar manner as the pixel structures of the first to eighth pixels P1, P2, P3, . . . , P8. A plurality of the pixels of the display panel 300 are repeatedly disposed using a unit pixel structure including the pixel structures of the first to eighth pixels P1, P2, P3, . . . , P8.
The first, third, sixth and eighth pixels P1, P3, P6 and P8 are disposed in a first pixel row PL1. The second, fourth, fifth and seventh pixels P2, P4, P5 and P7 are disposed in a second pixel row PL2. The ninth, eleventh, fourteenth and sixteenth pixels P9, P11, P14 and P16 are disposed in a third pixel row PL3. The tenth, twelfth, thirteenth and fifteenth pixels P10, P12, P13 and P15 are disposed in a fourth pixel row PL4. The first, second, ninth and tenth pixels P1, P2, P9 and P10 are disposed in a first pixel column PC1. The third, fourth, eleventh and twelfth pixels P3, P4, P11 and P12 are disposed in a second pixel column PC2. The sixth, fifth, fourteenth and thirteenth pixels P6, P5, P14 and P13 are disposed in a third pixel column PC3. The eighth, seventh, sixteenth and fifteenth pixels P8, P7, P16 and P15 are disposed in a fourth pixel column PC4. The pixels in the first and fourth pixel columns PC1 and PC4 may be red pixels, the pixels in the second pixel column PC2 may be green pixels, and the pixels in the third pixel column PC3 may be blue pixels.
The pixels P1, P2, P9 and P10 disposed in the first pixel column PC1 are electrically connected to the first and second data lines DL1 and DL2. The pixels P3, P4, P11 and P12 disposed in the second pixel column PC2 are electrically connected to the third and fourth data lines DL3 and DL4. The pixels P6, P5, P14 and P13 disposed in the third pixel column PC3 are electrically connected to the fifth and sixth data lines DL5 and DL6. The pixels P8, P7, P16 and P15 disposed in the fourth pixel column PC4 are electrically connected to the seventh and eighth data lines DL7 and DL8.
In addition, the pixels P1, P3, P6 and P8 disposed in the first pixel row PL1 and the pixels P2, P4, P5 and P7 disposed in the second pixel row PL2 are electrically connected to the first and second gate lines GL1 and GL2, which are electrically connected to each other. The pixels P9, P11, P14 and P16 disposed in the third pixel row PL3 and the pixels P10, P12, P13 and P15 disposed in the fourth pixel row PL4 are electrically connected to the third and fourth gate lines GL3 and GL4, which are electrically connected to each other.
When a first gate signal G1 is applied to the first and second gate lines GL1 and GL2, the liquid crystal capacitors of pixels P1, P3, P6 and P8 in the first pixel column PL1, and the liquid crystal capacitors of pixels P2, P4, P5 and P7 in the second pixel column PL2 are charged to the data voltages of the data signals provided to the first to eighth data lines DL1, DL2, DL3, . . . , DL8. Similarly, when a second gate signal G2 is applied to the third and fourth gate lines GL3 and GL4, the liquid crystal capacitors of pixels P9, P11, P14 and P16 in the third pixel column PL3, and the liquid crystal capacitors of pixels P10, P12, P13 and P15 in the fourth pixel column PL4 are charged to the data voltages of the data signals provided to the first to eighth data lines DL1, DL2, DL3, . . . , DL8.
As shown in
Referring to
As shown in
The timing controller 400 provides data signals to the data driver 500. The timing controller 400 repeatedly provides data corresponding to two horizontal lines to the data driver 500. The two horizontal lines are synchronized with a horizontally synchronized signal and a dot clock signal. For example, the timing controller 400 provides the data corresponding to the pixels in two pixel rows to the data driver 500.
The timing controller 400 provides a gate driving signal to the gate driver 150. The gate driving signal may include, for example, a clock signal and a vertically synchronized signal.
The data driver 500 converts the data corresponding to two horizontal lines received from the timing controller 400 during a horizontal cycle 1H into an analog data voltage. The analog data voltage is output to the M data lines DL1, DL2, . . . , DLM−1, and DLM. Two adjacent data lines are disposed between pixel columns, and data voltages having opposite polarities are applied to each of the two adjacent data lines. The data driver 500 may invert and output the polarities of the data voltages and apply the inverted data voltages to adjacent data lines during consecutive frames. For example, data line DL2 may have a negative polarity and data line DL3 may have a positive polarity during a first frame, and data line DL2 may have a positive polarity and data line DL3 may have a negative polarity in a second, subsequent frame.
The gate driver 150 generates n/2 gate signals and outputs the gate signals to n gate lines. A single gate signal may be simultaneously provided to two gate lines. For example, when two gate lines are electrically connected to each other, the gate driver 150 may simultaneously provide a single gate signal to the two gate lines. Alternatively, when the two gate lines are not connected to each other, the gate driver 150 may separately provide equivalent gate signals to each of the gate lines. Thus, each of the gate signals provided by the gate driver 150 turns on switching elements electrically connected to the gate lines.
Referring to
The data driver 500 converts data 1L/2L corresponding to a first horizontal line (e.g., a first pixel row) and a second horizontal line (e.g., a second pixel row) into data voltages, and outputs the data voltages to the M data lines DL1, DL2, . . . , DLM−1, DLM. The gate driver 150 then generates a first gate signal G1 having a pulse width corresponding to 1H, and outputs the first gate signal G1 to first and second gate lines GL1 and GL2. The pixels in the first and second pixel rows are then charged based on data 1L/2L.
The data driver 500 then converts data 3L/4L corresponding to a third horizontal line (e.g., a third pixel row) and a fourth horizontal line (e.g., a fourth pixel row) into data voltages, and outputs the data voltages to the M data lines DL1, DL2, . . . , DLM−1, and DLM. The gate driver 150 then generates a second gate signal G2 having a pulse width corresponding to 1H, and outputs the second gate signal G2 to third and fourth gate lines GL3 and GL4. The pixels in the third and fourth pixel rows are then charged based on data 3L/4L.
The data driver 500 then converts data (n−1)L/nL corresponding to an (n−1)-th horizontal line (e.g., an (n−1)-th pixel row) and an n-th horizontal line (e.g., an n-th pixel row) into data voltages, and outputs the data voltages to the M data lines DL1, DL2, . . . , DLM−1, DLM. The gate driver 150 then generates an (n/2)-th gate signal Gn/2 having a pulse width corresponding to 1H, and outputs the (n/2)-th gate signal Gn/2 to (n−1)-th and n-th gate lines GLn−1 and GLn. As a result, a frame cycle during which an image of a frame is displayed on the display panel 300 by the data driver 500 and the gate driver 150 may be about (n/2)×1H.
Referring to
Odd-numbered pixels in the first pixel row PL1 of the display panel 300 display a black image, and even-numbered pixels in the first pixel row PL1 display a color image. Odd-numbered pixels in the second and third pixel rows PL2 and PL3 display the color image, and even-numbered pixels in the second and third pixel rows PL2 and PL3 display the black image. Odd-numbered pixels in the fourth and fifth pixel rows PL4 and PL5 display the black image, and even-numbered pixels in the fourth and fifth pixel rows PL4 and PL5 display the color image. As explained above, the pixels in the pixel rows PL2, PL3, PL4, and PL5 alternately display the black image and the color image every two pixel rows. As a result, the (2+1) test pattern is displayed.
As shown in
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.
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| 2010-0073930 | Jul 2010 | KR | national |
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