Patent Grant
8310440
The present invention contains subject matter related to Japanese Patent Application No. 2008-287713 and Japanese Patent Application No. 2008-287714 filed in the Japanese Patent Office on Nov. 10, 2008 and Japanese Patent Application No. 2009-058068 filed in the Japanese Patent Office on Mar. 11, 2009, the entire contents of which are incorporated herein by reference.
1. Technical Field
The present invention relates to a method of driving an electrophoretic display device, an electrophoretic display device, and an electronic apparatus.
2. Related Art
For example, in JP-A-2007-206267, an electrophoretic display device, in which a voltage is not applied between a pixel electrode and a common electrode corresponding to a white display area of the first image but is applied only between a pixel electrode and a common electrode corresponding to a black display area (image component) for inverting the area so as to be removed as an entirely white display when an image displayed in a display unit is rewritten from the first image to the second image, has been disclosed.
When the image removal is performed by only driving pixels that form the image component as described above, it has been known that a thin afterimage is generated along the contour of the image component. In other words, occurrence of a burn-in phenomenon in a boundary portion of the image has been known. Such an afterimage is generated since an image of which the contour portion is raised is displayed due to generation of an electric field formed in the diagonal direction that crosses a pixel forming the contour and a pixel forming the background at the time of displaying an image.
Thus, a driving method in which an image is removed by performing image removal in all the pixels including pixels of which gray scales are not to be changed for preventing an afterimage of the previous image from remaining when the image is updated has been disclosed, for example, in JP-T-2007-512571.
However, in such a driving method, the electrophoretic particles are driven such that the final display gray scale is not changed also for the pixels of which the display is not changed. Accordingly, the electrophoretic particles are driven in the same manner as the entire display unit is rewritten, and there is a problem that the power consumption for updating an image increases.
An advantage of some aspects of the invention is that it provides a method of driving an electrophoretic display device, an electrophoretic display device, and an electronic apparatus that can remove an image without generating an afterimage (burn-in phenomenon) while suppressing the power consumption.
According to a first aspect of the invention, there is provided a method of driving an electrophoretic display device having a display unit that is formed of a plurality of pixels by pinching an electrophoretic element including electrophoretic particles between substrates forming one pair. The method includes setting an area that at least includes a pixel forming an image component that is formed to have a first gray scale and a pixel that is disposed to be adjacent to the pixel forming the contour of the image component and represents a second gray scale as an image removing area based on an image signal of an image that is displayed in the display unit and selectively changing the pixels that constitute the image removing area to have the second gray scale.
According to the above-described driving method, only the pixels that constitute the image removing area that is set broader than the image component are driven in the setting of the area and selectively changing of the pixels. Accordingly, the image can be removed without generating an afterimage (burn-in phenomenon) while suppressing the power consumption.
According to a second aspect of the invention, there is provided a method of driving an electrophoretic display device having a display unit that is formed of a plurality of pixels by pinching an electrophoretic element including electrophoretic particles between substrates forming one pair. The method includes: selectively changing a pixel that forms an image component formed to have a first gray scale to have a second gray scale based on an image signal of an image that is displayed in the display unit; and removing the image. The removal of the image includes setting an area that at least includes a pixel that forms the contour of the image component and a pixel that is disposed to be adjacent to the pixel that forms the contour and represents the second gray scale, as an afterimage removing area and selectively changing the pixels that constitute the afterimage removing area to have the second gray scale.
According to the above-described driving method, only the pixels that constitute the afterimage removing area are driven in the setting of the area as the afterimage removing area and selectively change the afterimage removing area, and accordingly, the afterimage can be removed while suppressing the power consumption. In addition, only the pixels forming the image component are driven in the selective changing of the pixel, and accordingly, an image can be removed while suppressing the power consumption. As a result, the power consumption in the removing of the image can be suppressed.
In the above-described method, it is preferable that the image removing area is set as the pixel that forms the image component and the pixel that is disposed to be adjacent to a pixel that forms the contour of the image component and represents the second gray scale.
In such a case, the image displaying area that is formed by the image component and a band-shaped area corresponding to one pixel which frames the contour of the image is set as the image removing area. Accordingly, only a minimum number of the pixels are driven in the setting of the area as the image removing area and changing of the pixels. As a result, the image can be removed without generating any afterimage while suppressing the power consumption further.
In the above-described method, it is preferable that a value acquired by multiplying a voltage applied to the electrophoretic element by a time interval of the application of the voltage in the setting of the area and selectively changing the pixels to have the second gray scale is set to be smaller than a value acquired by multiplying a voltage applied to the electrophoretic element and a time interval of application of the voltage in the setting of the area as the image removing area and selectively changing the pixels to have the second gray scale.
In such a case, the load of the electrophoretic element can be suppressed in the setting of the area as the afterimage removing area and selectively changing the pixels. Accordingly, the balance of the electric potential of the electrophoretic element over the entire area of the display unit can be maintained to be approximately uniform. As a result, generation of unevenness in the displayed image can be prevented.
According to a third aspect of the invention, there is provided an electrophoretic display device including: a display unit that is formed of a plurality of pixels by pinching an electrophoretic element including electrophoretic particles between substrates forming one pair; and a control unit that controls the display unit. The control unit sets an area that at least includes a pixel forming an image component that is formed to have a first gray scale and a pixel that is disposed to be adjacent to a pixel forming the contour of the image component and represents a second gray scale as an image removing area based on an image signal of an image that is displayed in the display unit and selectively changes the pixels that constitute the image removing area to have the second gray scale, when an image of the display unit is to be removed.
According to the above-described electrophoretic display device, only the pixels that constitute the image removing area that is set broader than the image component are driven when the image is removed. Accordingly, an electrophoretic display device, which can remove the image without generating an afterimage while suppressing the power consumption, can be provided.
In the above-described electrophoretic display device, it is preferable that the image removing area is set as the pixel that forms the image component and the pixel that is disposed to be adjacent to a pixel that forms the contour of the image component and represents the second gray scale.
In such a case, by setting the image displaying area that is formed by the image component and a band-shaped area corresponding to one pixel which frames the contour of the image as the image removing area, only a minimum number of the pixels are driven for removing the image. As a result, an electrophoretic display device, which can remove the image without generating any afterimage while suppressing the power consumption further, can be provided.
According to a fourth aspect of the invention, there is provided an electronic apparatus that includes the above-described electrophoretic display device.
According to the above-described electronic apparatus, only the pixels that constitute the image removing area that is set broader than the image component are driven when the image is removed. Accordingly, an electronic apparatus, which can remove the image without generating an afterimage while suppressing the power consumption, can be provided.
The invention will be described with reference to the accompanying drawings, wherein like numbers reference like elements.
Hereinafter, an electrophoretic display device according to a first embodiment of the invention will be described with reference to the accompanying drawings. In this embodiment, an electrophoretic display device that is driven in an active matrix mode will be described. This embodiment represents one embodiment of the invention. Thus, this embodiment does not limit the scope of the invention and may be arbitrarily changed within the scope of the technical idea of the invention. In the drawings below, the scale or the number of each structure is different from that of the actual structure for ease of understanding of each configuration.
Configuration of Electrophoretic Display Device
The electrophoretic display device 100 includes a display unit 5 in which a plurality of pixels 40 is arranged. In the vicinity of the display unit 5, a scanning line driving circuit 61, a data line driving circuit 62, a controller (control unit) 63, and a common power source modulating circuit 64 are disposed. The scanning line driving circuit 61, the data line driving circuit 62, and the common power source modulating circuit 64 are connected to the controller 63. The controller 63 comprehensively controls the above-described members based on image signal and a synchronization signal that are supplied from an upper-level apparatus.
In the display unit 5, a plurality of scanning lines 66 that extends from the scanning line driving circuit 61 and a plurality of data lines 68 that extends from the data line driving circuit 62 are formed. In addition, pixels 40 are disposed in correspondence with intersections of the plurality of scanning lines and the plurality of data lines.
The scanning line driving circuit 61 is connected to the pixels 40 through m scanning lines 66 (Y1, Y2, . . . , Ym). The scanning line driving circuit 61 sequentially selects the scanning lines 66 of the 1st row to the m-th row under the control of the controller 63 and supplies a selection signal that defines an ON-timing of a driving TFT 41 (see
The data line driving circuit 62 is connected to the pixels 40 through n data lines 68 (X1, X2, . . . , Xn) and supplies an image signal that defines one bit image data corresponding to each pixel 40 to the pixel 40 under the control of the controller 63.
In addition, in this embodiment, it is assumed that the data line driving circuit supplies a low-level image signal to the pixel 40 in the case where corresponding image data (pixel data) is defined as “0” and supplies a high-level image signal to the pixel 40 in the case where corresponding image data (pixel data) is defined as “1”.
In the display unit 5, a low-electric potential power source line 49, a high-electric potential power source line 50, a common electrode wiring 55, a first control line 91, and a second control line 92 that extend from the common power source modulating circuit 64 are disposed, and each wiring is connected to the pixels 40. The common power source modulating circuit 64 generates various signals to be supplied to the above-described wirings and electrically connects or disconnects (high impedance state) the wirings, under the control of the controller 63.
In the pixel 40, as shown in
The driving TFT 41 is a pixel switching element that is configured by an N-MOS (negative metal oxide semiconductor) transistor. The gate terminal of the driving TFT 41 is connected to the scanning line 66, the source terminal of the driving TFT 41 is connected to the data line 68, and the drain terminal of the driving TFT 41 is connected to a data input terminal N1 of the latch circuit 70. The switching circuit 80 is connected to the data output terminal N2 and the data input terminal N1 of the latch circuit 70 and the pixel electrode 35. In addition, between the pixel electrode 35 and the common electrode 37, the electrophoretic element 32 is pinched.
The latch circuit 70 includes a transfer inverter 70t and a feedback inverter 70f. Both the transfer inverter 70t and the feedback inverter 70f are C-MOS inverters. The transfer inverter 70t and the feedback inverter 70f form a loop structure in which, to each input terminal of one of the transfer inverter and the feedback inverter, the output terminal of the other is connected. In addition, to each inverter, a power source voltage is supplied from the high-electric potential power source line 50 that is connected through a high-electric potential power source terminal PH and the low-electric potential power source line 49 that is connected through a low-electric potential power source terminal PL.
The transfer inverter 70t includes a P-MOS transistor 71 and an N-MOS transistor 72 of which the drain terminals are connected to the data output terminal N2. The source terminal of the P-MOS transistor 71 is connected to the high-electric potential power source terminal PH, and the source terminal of the N-MOS transistor 72 is connected to the low-electric potential power source terminal PL. The gate terminals (the input terminal of the transfer inverter 70t) of the P-MOS transistor 71 and the N-MOS transistor 72 are connected to the data input terminal N1 (the output terminal of the feedback inverter 70f).
The feedback inverter 70f includes a P-MOS transistor 73 and an N-MOS transistor 74 of which the drain terminals are connected to the data input terminal N1. The gate terminals (the input terminal of the feedback inverter 70f) of the P-MOS transistor 73 and the N-MOS transistor 74 are connected to the data output terminal N2 (the output terminal of the transfer inverter 70t).
When pixel data of “1” (an image signal having a high level) is stored in the latch circuit 70, a low-level signal is output from the data output terminal N2 of the latch circuit 70. On the other hand, when pixel data of “0” (an image signal having a low level) is stored in the latch circuit 70, a high-level signal is output from the data output terminal N2.
The switching circuit 80 is configured to include a first transmission gate TG1 and a second transmission gate TG2.
The first transmission gate TG1 is configured by an N-MOS transistor 81 and a P-MOS transistor 82. The source terminals of the N-MOS transistor 81 and P-MOS transistor 82 are connected to the first control line 91, and the drain terminals of the N-MOS transistor 81 and P-MOS transistor 82 are connected to the pixel electrode 35. In addition, the gate terminal of the N-MOS transistor 81 is connected to the data input terminal N1 (the drain terminal of the driving TFT 41) of the latch circuit 70, and the gate terminal of the P-MOS transistor 82 is connected to the data output terminal N2 of the latch circuit 70.
The second transmission gate TG2 is configured by an N-MOS transistor 83 and a P-MOS transistor 84. The source terminals of the N-MOS transistor 83 and P-MOS transistor 84 are connected to the second control line 92, and the drain terminals of the N-MOS transistor 83 and the P-MOS transistor 84 are connected to the pixel electrode 35. In addition, the gate terminal of the N-MOS transistor 83 is connected to the data output terminal N2 of the latch circuit 70, and a gate terminal of the P-MOS transistor 84 is connected to the data input terminal N1 of the latch circuit 70.
Here, in the case where a pixel data of “1” (an image signal having the high level) is stored in the latch circuit 70, and a low-level signal is output from the data output terminal N2, the first transmission gate TG1 is in the ON state, and accordingly, an electric potential S1, which is supplied through the first control line 91, is input to the pixel electrode 35. On the other hand, in the case where a pixel data of “0” (an image signal having the low level) is stored in the latch circuit 70, and a high-level signal is output from the data output terminal N2, the second transmission gate TG2 is in the ON state, and accordingly, an electric potential S2, which is supplied through the second control line 92, is input to the pixel electrode 35.
The electrophoretic display device 100 has a configuration in which an electrophoretic element 32 formed by arranging a plurality of microcapsules 20 is pinched between a component substrate 30 and an opposing substrate 31. In the display unit 5, a plurality of the pixel electrodes 35 is formed so as to be arranged on the electrophoretic element 32 side of the component substrate 30, and the electrophoretic element 32 is bonded to the pixel electrode 35 through an adhesive agent layer 33.
The component substrate 30 is a substrate that is formed from glass, plastic, or the like. Since the component substrate 30 is disposed on a side opposite to the image displaying surface, the component substrate 30 may not be configured to be transparent. The pixel electrode 35 is an electrode that is acquired by stacking a nickel plate and a gold plate on a Cu thin film in the mentioned order or is formed from Al, ITO (indium tin oxide), or the like. Although not shown in the figure, the scanning line 66, the data line 68, the driving TFT 41, the latch circuit 70, and the like that are shown in
The opposing substrate 31 is a substrate that is formed from glass, plastic, or the like. Since the opposing substrate 31 is disposed on the side of the image displaying surface, the opposing substrate 31 is formed as a transparent substrate. On the electrophoretic element 32 side of the opposing substrate 31, a flat common electrode 37 (opposing electrode) is formed so as to face the plurality of pixel electrodes 35. In addition, the electrophoretic element 32 is disposed on the common electrode 37. The common electrode 37 is a transparent electrode that is formed of MgAg, ITO, IZO (indium zinc oxide), or the like.
In addition, the electrophoretic element 32 is formed on the opposing substrate 31 side in advance. Generally, the electrophoretic element 32 is handled as an electrophoretic sheet that includes up to the adhesive agent layer 33. In the manufacturing process, the electrophoretic sheet is handled in a state in which a protection peel-off sheet is attached to the surface of the adhesive agent layer 33. Then, by attaching the electrophoretic sheet, from which the peel-off sheet is detached, to the component substrate 30 (on which the pixel electrode 35 and various circuits are formed) that is separately manufactured, the display unit 5 is formed. Accordingly, the adhesive agent layer 33 is placed only on the pixel electrode 35 side.
The microcapsule 20, for example, has a particle diameter of about 50 μm and is a sphere-shaped body in which a dispersion medium 21, a plurality of white particles (electrophoretic particles) 27, and a plurality of black particles (electrophoretic particles) 26 are enclosed. The microcapsule 20, as shown in
The outer shell part (wall film) of the microcapsule 20 is formed of a transparent high molecular resin such as an acryl resin including polymethylmethacrylate, polyethylmethacrylate, or the like, urea resin, gum Arabic, or the like.
The dispersion medium 21 is a liquid that disperses the white particles 27 and the black particles 26 into the microcapsule 20. As the dispersion medium 21, water; an alcohol-based solvent such as methanol, ethanol, isopropanol, butanol, octanol, or methyl cellosolve; esters such as ethyl acetate or butyl acetate; ketones, such as acetone, methylethylketone, or methylisobutylketone; aliphatic hydrocarbon such as pentane, hexane, or octane; alicyclic hydrocarbon such as cyclohexane or methylcyclohexane; aromatic hydrocarbon such as benzene, toluene, or benzene having a long-chain alkyl group including xylene, hexylbenzene, heptylbenzene, octylbenzene, nonylbenzene, decylbenzene, undecylbenzene, dodecylbenzene, tridecylbenzene, or tetradecylbenzene; halogenated hydrocarbon such as methylene chloride, chloroform, carbon tetrachloride, or 1,2-dichloroethane; carboxylate; or other kinds of oils can be used. The above-described materials may be used in the form of a single material or a mixture. Further, a surfactant, or the like, may be added to the above-described material.
The white particles 27 are particles (polymers or colloids) made of white pigment such as titanium dioxide, zinc oxide, or antimony trioxide and, for example, are used in a negatively charged state. The black particles 26 are particles (polymer particles or colloids) made of black pigment such as aniline black or carbon black and, for example, are used in a positively charged state.
In addition, a charge control agent containing particles of an electrolyte, a surfactant, metal soap, a resin, rubber, oil, varnish, a compound, or the like; a dispersant such as a titanium-based coupling agent, an aluminum-based coupling agent, and a silane-based coupling agent; a lubricant; a stabilizing agent; or the like may be added to the above-described pigment, as needed.
Instead of the black particles 26 and the white particles 27, for example, pigment of a red color, a green color, a blue color, or the like may be used. Under such a configuration, the red color, the green color, the blue color, or the like may be displayed in the display unit 5.
In the case of the white display shown in
In the case of the black display shown in
In the electrophoretic display device 100, an image signal is stored in the latch circuit 70 as an electric potential by inputting the image signal to the data input terminal N1 of the latch circuit 70 through the driving TFT 41. Then, either the first control line 91 or the second control line 92 is connected to the pixel electrode 35 by the switching circuit 80 that operates in accordance with the electric potential that is output from the data output terminal N2 of the latch circuit 70. Accordingly, the electric potential corresponding to the image signal is input to the pixel electrode 35. Thus, as shown in
The controller 63 includes a control circuit 161 as a CPU (central processing unit), an EEPROM (electrically-erasable and programmable read-only memory; memory unit) 162, a voltage generating circuit 163, a data buffer 164, a frame memory 165, a memory control circuit 166, and an image removing area setting circuit 167.
The control circuit 161 generates control signals (timing pulses) such as a clock signal, a horizontal synchronization signal, and a vertical synchronization signal and supplies these control signals to circuits that are disposed on the periphery of the control circuit 161.
In the EEPROM 162, setting values and the like needed for the control circuit 161 to control the operation of each circuit is stored. In the EEPROM 162, preset image information that is used for the display of the operation state of the electrophoretic display device may be stored.
The voltage generating circuit 163 is a circuit that supplies driving voltages to the scanning line driving circuit 61, the data line driving circuit 62, and the common power source modulating circuit 64.
The data buffer 164 is an interface unit of the controller 63 for a higher level apparatus. The data buffer 164 maintains the image data D that is input from the higher-level apparatus and transmits the image data D to the control circuit 161.
The frame memory 165 has a memory space in which a read operation or a write operation can be performed in correspondence with the arrangement of the pixels 40 of the display unit 5. The memory control circuit 166 expands the image data D, which is supplied from the control circuit 161, in correspondence with the arrangement of the pixels of the display unit 5 in accordance with a control signal and writes the expanded image data into the frame memory 165. The frame memory 165 sequentially transmits a data group that is constituted by stored image data D to the data line driving circuit 62 as image signals.
The data line driving circuit 62 latches one line of the image signals that are transmitted from the frame memory 165 based on a control signal that is supplied from the control circuit 161. Then, the data line driving circuit 62 supplies the latched image signals to the data line 68 in synchronization with the sequential selection operation of the scanning line driving circuit 61 for the scanning line 66.
The image removing area setting circuit 167 sets an image removing area constituted by the pixels 40 that are driven at the time of image removal based on the image data D that is expanded into the frame memory 165 and outputs pixel information that constitutes the image removing area to the control circuit 161.
Driving Method
Next, a driving method relating to the image update of the electrophoretic display device 100 will be described. According to this embodiment, as an example, a driving method for a case where a square image is displayed, and then, update to a rectangular image having the horizontal side longer than the vertical side is made will be described.
Image Displaying Step
First, the image displaying step S101 will be described. The image displaying step S101 is a step for displaying an image in the display unit 5.
In
In
In addition, in
In
According to the driving method of this embodiment, before an image is displayed, image signals are input to the latch circuits 70 (70a, 70b, and 70c) of all the pixels 40 (40A, 40B, and 40C).
As shown in
When the image signals are input to the latch circuits 70a, 70b, and 70c, the electric potential Vdd of the high-electric potential power source line 50 is set to a high level (VH) that is used for image display, and the electric potential Vss of the low-electric potential power source line 49 is set to a low level (VL). Accordingly, the electric potential of the data input terminal N1a of the pixel 40A becomes the high level (VH; Vdd), and the electric potential of the data output terminal N2a of the pixel 40A becomes the low level (VL; Vss). In addition, the electric potentials of the data input terminals N1b and N1c of the pixels 40B and 40C become the low level (VL; Vss), and the electric potentials of the data output terminals N2b and N2c of the pixels 40B and 40C become the high level (VH; Vdd).
Accordingly, when the image signals are input to the latch circuits 70a, 70b, and 70c of the pixels 40A, 40B, and 40C, as shown in
In the pixel 40A to which the high-level (H) image signal is input, the electric potential of the data input terminal N1a becomes the high level (VH; Vdd), and the electric potential of the data output terminal N2a becomes the low level (VL; Vss). Accordingly, the transmission gate TG1a of the switching circuit 80a is in the ON state, and the high-level electric potential VH is supplied from the first control line 91 to the pixel electrode 35a.
On the other hand, in the pixels 40B and 40C to which the low-level (L) image data is input, the electric potentials of the data input terminals N1b and N1c become the low level (L), and the electric potentials of the data output terminals N2b and N2c become the high level (H). Accordingly, the transmission gate TG2b of the switching circuit 80b is in the ON state, and the low-level electric potential VL is supplied from the second control line 92 to the pixel electrodes 35b and 35c.
In addition, a pulse-shaped signal in which a period of the high level (VH) and a period of the low level (VL) are periodically repeated is input to the common electrode 37.
In such a case, a voltage corresponding to an electric potential difference between the pixel electrode 35a and the common electrode 37 is applied to the electrophoretic element 32 during the period in which the common electrode 37 is the low level (VL). Accordingly, as shown in
In addition, a voltage corresponding to electric potential differences between the pixel electrodes 35b and 35c and the common electrode 37 is applied to the electrophoretic element 32 during the period in which the common electrode 37 is at the high level (VH). Accordingly, as shown in
In the driving method according to this embodiment, a pulse-shaped signal in which the high level (VH) and the low level (VL) are periodically repeated is input to the common electrode 37 for a plurality of periods. Such a driving method is referred to as “common swing driving” in the description here. The common swing driving is defined as a driving method in which a pulse, in which the high level (VH) and the low level (VL) are repeated, is applied to the common electrode 37 for at least one or more periods for displaying an image. In addition, it is preferable that the frequency and the number of the periods in the common swing driving are appropriately set based on the specifications and the characteristics of the electrophoretic element 32.
When the square image P1 is displayed, the first control line 91, the second control line 92, and the common electrode 37 are electrically disconnected from each other by the common power source modulating circuit 64 so as to be in the high-impedance state. In addition, the pixel electrodes 35 (35a, 35b, and 35c) to which the voltages are supplied from the first control line 91 and the second control line 92 are also in the high-impedance state, and whereby the image displaying step S101 is completed. At this moment, the latch circuits 70 (70a, 70b, and 70c) are driven, and the input image signals are stored therein.
Image Removing Step
Next, the image removing step S111 will be described. However, before the description is made, a case where only the image P1 is selectively removed by driving only the pixel 40(A) that forms the image P1 will be described.
As shown in
Then, when only the image P1 is removed, only the contour portion that is raised remains to be the afterimage P2. Thus, according to this embodiment, the image P1 is removed by using the driving method described below.
The image removing step S111 is a step for removing the image P1 by setting an image removing area that is constituted by an area for forming the image P1 and an area framing the contour of the image P1 and driving only the pixels 40 (40A and 40B) that constitute the image removing area.
Here, a method of setting the image removing area R will be described. The image removing area setting circuit 167 extracts the pixel 40 (40B), which is disposed on the background side to be adjacent to the pixel 40 (40A) that forms the contour of the image P1, from the image data D that is expanded in the frame memory 165. The pixel 40 (40B) extracted as described above configures a band-shaped area, which has a width corresponding to one pixel, framing the contour of the image P1. These pixels 40 (40B), for example, are extracted by using a general technique that is employed by image processing software.
Then, the image removing area setting circuit 167 sets an area that is formed by the pixel 40 (40A) forming the image P1 and the pixel 40 (40B) framing the contour of the image P1 as the image removing area R. The set image removing area R, as shown in
The pixel information that configures the image removing area R is output from the image removing area setting circuit 167 to the control circuit 161, and image data D for image removal is generated by the control circuit 161. The image data D for image removal that is generated by the control circuit 161 is expanded into the frame memory 165, and then is input to the latch circuits 70 (70a, 70b, and 70c) of the pixels 40 (40A, 40B, and 40C).
According to this embodiment, the pixels 40 (40B) framing the image P1 are extracted from the image data D after being expanded into the frame memory 165. However, the pixel 40 (40B) framing the contour of the image P1 may be configured to be extracted by analyzing the image data D before expansion by using the control circuit 161. In such a case, the process from the setting of the image removing area R to generating of the image data D for image removal is performed consistently by the control circuit 161.
The transmission gates TG1 (TG1a and TG1b) of the pixels 40 (40A and 40B) to which the high-level (H) image signal is input are in the ON state. On the other hand, the transmission gate TG2 (TG2c) of the pixel 40 (40C) to which the low-level (L) image signal is input is in the ON state.
When the image signals are input to the latch circuits 70 (70a, 70b, and 70c), the electric potentials of the high-electric potential power source line 50 and the low-electric potential power source line 49 are set to the electric potentials (VH and VL) for image display.
Accordingly, when the image signal for the image removal is input, as shown in
The pixel electrodes 35 (35a and 35b) of the pixels 40 (40A and 40B) having the latch circuits 70 to which the high-level (H) image signals are input are connected to the first control line 91 and are supplied with the low-level (VL) electric potential. On the other hand, the pixel electrode 35 (35c) of the pixel 40 (40C) having the latch circuit 70 to which the low-level (L) image signal is input is connected to the second control line 92 and is in the high-impedance state.
Accordingly, in the pixels 40 (40A and 40B) that constitute the image removing area R to which the high-level (H) image signals are input, a voltage corresponding to an electric potential difference between the pixel electrodes 35 (35a and 35b) and the common electrode 37 are applied to the electrophoretic element 32 during a period in which the high-level (VH) electric potential is supplied to the common electrode 37. Accordingly, in the image removing area R, the black particles 26 move to the pixel electrode 35 side, and the white particles 27 move to the common electrode 37 side, whereby the image P1 is removed.
At this moment, the pixel 40 (40B) that frames the contour of the image P1 is driven. Accordingly, even in an area raised from the contour of the image P1, the black particles 26 move to the pixel electrode 35 side, and the white particles 27 move to the common electrode 37 side. Therefore, any afterimage is not generated after the image P1 is removed.
During a period in which the low-level (VL) electric potential is supplied to the common electrode 37, the pixel electrodes 35 (35a and 35b) and the common electrode 37 have the same electric potential, and accordingly, there is little influence on the movement of the black particles 26 and the white particles 27.
On the other hand, in the pixel 40 (40C) to which the low-level (L) image signal is input, the pixel electrode 35 (35c) is in the high-impedance state. Accordingly, even when a pulse is supplied to the common electrode 37, there is little influence on the movement of the black particles 26 and the white particles 27, and whereby the white display is maintained.
Accordingly, as shown in
In addition, a same signal as the pulse that is input to the common electrode 37 may be configured to be input to the second control line 92. In such a case, in the pixel 40 (40C) to which the low-level image signal is input, the pixel electrode 35 (35c) and the common electrode 37 have the same electric potential. Accordingly, there is little influence on the movement of the black particles 26 and the white particles 27, and whereby the white display of the background can be maintained.
Here, for example, the signal that is input to the common electrode 37 in the image removing step S111, is a signal in which pulses, of which the high-level electric potential (VH) is 15 V, the low-level electric potential (VL) is 0 V, and the pulse width and the number of the pulses are 20 ms×30 pulses and 200 ms×4 pulses, are continuous. When the image P1 is removed, as shown in
Update Image Displaying Step
The update image displaying step S121 is a step for displaying an update image P11 shown in
When the process proceeds to the update image displaying step S121, the image data D for image update is output from the control circuit 161 to the frame memory 165. Then, after the image data D is expanded in the frame memory 165 as an image signal for each pixel 40, the image signal is input to the latch circuit 70 of each pixel 40.
All the pixels 40A, 40B, and 40C are pixels 40 that form the update image P11, and accordingly, as shown in
The transmission gates TG1 (TG1a, TG1b, and TG1c) of the pixels 40 (40A, 40B, and 40C) having the latch circuits 70, to which the high-level (H) image signals are input, are in the ON state. On the other hand, the transmission gate TG2 of the pixel 40 having the latch circuit 70 to which the low-level (L) image signal is input is in the ON state.
When the image signals are input to the latch circuits 70, the electric potentials (Vdd and Vss) of the high-electric potential power source line 50 and the low-electric potential power source line 49 are set to the electric potentials (VH and VL) for image display. Then, as shown in
The pixel electrodes 35 (35a, 35b, and 35c) of the pixels 40 (40A, 40B, and 40C) having the latch circuits 70 to which the high-level (H) image signals are input are connected to the first control line 91 and are supplied with the high-level (VH) electric potentials.
On the other hand, the pixel electrode 35 of the pixels 40 having the latch circuit 70 to which the low-level (L) image signal is input is connected to the second control line 92 and is supplied with the low-level (VL) electric potential.
Accordingly, the black display is represented by the pixels 40 (40 A, 40 B, and 40 C) to which the high-level (H) image signals are input, and the update image P11, shown in
As shown in
When the update image P11 is displayed, the first control line 91, the second control line 92, and the common electrode 37 are in the high-impedance state, and the update image displaying step S121 is completed.
When the image is to be updated consecutively, the image removing step S111 and the update image displaying step S121 are repeatedly performed.
According to the electrophoretic display device 100 using the above-described driving method, the following advantages can be acquired.
First, the image removing area R that is configured by the pixels 40 (40A and 40B) that form the image P1 and the pixel 40 (40C) that configures the band-shaped area, which frames the contour of the image P1, corresponding to one pixel is set. Accordingly, the number of pixels driven in the image removing step S111 becomes a minimum. Therefore, the image P1 can be removed without generating any afterimage while suppressing the power consumption.
In addition, it is preferable that the image removing area R is set in accordance with the generation pattern of the afterimage that is different depending on the characteristics of the electrophoretic element 32.
For example, an area that is expanded from the image P1 by two pixels or more may be set as the image removing area R. In such a case, the number of the pixels to be driven is increased, and the advantage in the viewpoint of the power consumption is degraded. However, in such a case, the pixels 40 in the broader range are driven in the image removing step S111, and accordingly, generation of the afterimage can be prevented more assuredly.
In addition, the value acquired by multiplying the voltage of the pulse applied to the electrophoretic element 32 by the time interval of application of the voltage may be changed as is necessary based on the used temperature level, the applied voltage, the individual difference of the electrophoretic sheets, or the like.
Next, an electrophoretic display device according to a second embodiment of the invention will be described.
The electrophoretic display device 110 according to the second embodiment has a pixel circuit that is different from that according to the first embodiment. In particular, the electrophoretic display device 110 includes a pixel circuit (a so-called 1T1C type) that is configured by one driving TFT and a holding capacitor, which is simpler than that of the first embodiment. Other configurations and the driving method according to the second embodiment are the same as those according to the first embodiment on the whole. Accordingly, parts of the second embodiment that are different from those of the first embodiment will be described in detail, and description of other configurations will be omitted appropriately. In addition, a constituent part that is the same as that of the first embodiment will be described with a same reference sign attached thereto.
Configuration of Electrophoretic Display Device
First, the entire configuration of the electrophoretic display device according to this embodiment will be described.
As shown in
In the display unit 5, pixels 40 of m rows×n columns are arranged in a matrix shape (in a two-dimensional plane). In addition, in the display unit 5, m scanning lines 66 (that is, Y1, Y2, . . . , Ym) and n data lines 68 (that is, data lines X1, X2, . . . , Xn) are disposed so as to intersect each other. In particular, the m scanning lines 66 extend in the row direction (that is, direction X), and the n data lines 68 extend in the column direction (that is, direction Y). The pixels 40 are disposed in correspondence with intersections of the m scanning lines 66 and the n data lines 68.
The controller 10 controls the operations of the scanning line driving circuit 61, the data line driving circuit 62, and the common electrode modulating circuit 11. The controller 10 supplies timing signals such as a clock signal and a start pulse to each circuit.
The scanning line driving circuit 61 sequentially supplies scanning signals as pulses to the scanning lines Y1, Y2, . . . , Ym based on timing signals that are supplied from the controller 10. The data line driving circuit 62 supplies image signals to the data lines X1, X2, . . . , Xn based on timing signals supplied from the controller 10. The image signal takes binary levels of a high electric-potential level (hereinafter, referred to as a “high level”, for example, of 5 V) or a low electric-potential level (hereinafter, referred to as a “low level”, for example, of 0 V).
The common electrode modulating circuit 11 supplies the common electric potential Vcom to the common electrode wiring 55 and supplies the power source electric potential Vs to a holding capacitor line 56. Here, the “common electrode wiring 55” and the “holding capacitor line 56” configures an example of a “driving unit” according to an embodiment of the invention.
In addition, various signals are input to or output from the controller 10, the scanning line driving circuit 61, the data line driving circuit 62, and the common electrode modulating circuit 11. However, description of signals not particularly relating to this embodiment will be omitted.
As shown in
The driving TFT 41, for example, is configured by an N-type transistor. The driving TFT 41 has the gate electrically connected to the scanning line 66, the source electrically connected to the data line 68, and the drain electrically connected to the pixel electrode 35 and the holding capacitor 42.
The driving TFT 41 outputs an image signal, which is supplied from the data line driving circuit 62 (see
The image signal is supplied to the pixel electrode 35 from the data line driving circuit 62 through the data line 68 and the driving TFT 41. The pixel electrode 35 is disposed so as to face the common electrode 37 through the electrophoretic element 32.
The common electrode 37 is electrically connected to the common electrode wiring 55 to which the common electric potential Vcom is supplied.
The electrophoretic element 32 is configured by a plurality of microcapsules that is formed to include electrophoretic particles, respectively.
The holding capacitor 42 is configured by one pair of electrodes disposed to face each other through a dielectric film. One electrode of the holding capacitor 42 is electrically connected to the pixel electrode 35 and the driving TFT 41, and the other electrode of the holding capacitor 42 is electrically connected to the holding capacitor line 56. The image signal can be maintained for a predetermined period by the holding capacitor 42.
Driving Method
Next, the operation for updating a displayed image at the time of the operation of the electrophoretic display device 110 will be described.
Image Displaying Step
The driving method according to the second embodiment also includes the image displaying step S101, the image removing step S111, and the update image displaying step S121 that have been described with reference to
In the state shown in
Accordingly, the black electrophoretic particles move to the common electrode 37 side only in the area a, and the first image as shown in
In other words, in the image displaying step S101, image data on the basis of an image signal that defines the first image is written into each pixel, and accordingly, the first image is displayed in the display unit 5.
Image Removing Step
Next, before the displayed image is changed from the first image to the second image (see
Accordingly, the black electrophoretic particles move to the pixel electrode 35 side only in the area a, and whereby the first diagram is removed. In addition, it is preferable that the width (that is, a distance between the outer edge of the area a and the outer edge of the area c) of the area c is a width corresponding to the size of one pixel.
In other words, in the image removing step S111, an area that includes the pixels of the area a forming the diagram (image component) of the black display and pixels of the area c that is disposed to be adjacent to pixels that form the contour of the image component (area a) and represents the white display is set as the image removing area. Then, the pixel constituting the image removing area is selectively changed to have the white display.
Next, as shown in
Update Image Displaying Step
Next, as shown in
In other words, in the update image displaying step S121, image data on the basis of the image signal that defines the second image is written into each pixel, and accordingly, the second image is displayed in the display unit 5.
According to the driving method of the second embodiment described above, in order to remove the area a in which the black display is represented, an area acquired by adding the area c that surrounds the area a to the area a is removed as the image removing area in the image removing step. In other words, an area that includes the pixels of the area a that forms the diagram (image component) of the black display and the pixels of the area c disposed to be adjacent to the pixels forming the contour of the image component (area a) and which represent the white display is set as the image removing area, and the pixels constituting the image removing area are selectively changed to represent the white display.
Accordingly, even in the electrophoretic display device 110 that includes a pixel circuit including one driving TFT and the holding capacitor, the burn-in phenomenon that occurs in a boundary portion between the area a and the area c, that is, the afterimage formed along the contour of the area a, which has been described with reference to
In addition, in the image removing step, the image removal is performed for the area acquired by adding the area c to the area a as the image removing area. Accordingly, the power consumption can be suppressed, compared to a general driving method in which even the pixels having no change in display are driven for display.
As a result, according to this driving method, an image can be removed without generating the afterimage (burn-in phenomenon) while suppressing the power consumption.
In addition, in
Next, the operation for updating a displayed image at the time of the operation of an electrophoretic display device according to the modified example of this embodiment will be described with reference to
In this modified example, after the inversion removal period (the image removing step S111), instead of the entirely white removal period (the entire removal step S112), a removal period (removal step S113) in which the entirely white display and the entirely black display are repeatedly performed in a relatively short period is provided. In addition, it is preferable that repetition of the entirely white display and the entirely black display is performed in the period of one millisecond to ten milliseconds.
In the removal step S113, the entirely white display and the entirely black display are repeated in the relatively short period, and accordingly, the electrophoretic particles are agitated within the dispersion medium relatively well. Accordingly, a decrease in the afterimage generated at the time of image removal or a transient afterimage can be achieved.
Next, a driving method of an electrophoretic display device, according to a third embodiment of the invention will be described.
The driving method according to the third embodiment is a driving method in which the electrophoretic display device 100 described in the first embodiment is used. However, the driving method according to the third embodiment is different from that according to the first embodiment. In other words, in the third embodiment, only the driving method is different from that in the first embodiment. The configuration of the electrophoretic display device and the like other than the driving method are the same as those of the first embodiment.
In particular, the image removing step is configured by two steps of a partial removal step and an afterimage removing step, which is different from that of the first embodiment. Other driving steps are the same as those of the first embodiment on the whole.
Thus, parts of the third embodiment that are different from those of the first embodiment will be described in detail, and description of other configurations will be omitted appropriately. In addition, to each constituent part that is the same as that of the first embodiment, a same reference sign is attached for description.
Driving Method
Next, a driving method relating to image update of the electrophoretic display device 100 (
Image Displaying Step
First, the image displaying step S101 will be described. The image displaying step S101 is a step for displaying an image in the display unit 5.
In
In addition, in
In
According to the driving method of this embodiment, before an image is displayed, image signals are input to the latch circuits 70 (70a and 70b) of the pixels 40 (40A and 40B).
As shown in
When the image signals are input to the latch circuits 70a and 70b, the electric potential Vdd of the high-electric potential power source line 50 is set to the high level (VH) that is used for image display, and the electric potential Vss of the low-electric potential power source line 49 is set to a low level (VL). Accordingly, the electric potential of the data input terminal N1a of the pixel 40A becomes the high level (VH; Vdd), and the electric potential of the data output terminal N2a of the pixel 40A becomes the low level (VL; Vss). In addition, the electric potential of the data input terminal N1b of the pixel 40B becomes the low level (VL; Vss), and the electric potential of the data output terminal N2b of the pixel 40B becomes the high level (VH; Vdd).
Accordingly, when the image signals are input to the latch circuits 70a, and 70b of the pixels 40A and 40B, as shown in
In the pixel 40A to which the high-level (H) image signal is input, the electric potential of the data input terminal N1a becomes the high level (VH; Vdd), and the electric potential of the data output terminal N2a becomes the low level (VL; Vss). Accordingly, the transmission gate TG1a of the switching circuit 80a is in the ON state, and the high-level electric potential VH is supplied from the first control line 91 to the pixel electrode 35a.
On the other hand, in the pixel 40B to which the low-level (L) image signals are input, the electric potential of the data input terminal N1b becomes the low level (L), and the electric potential of the data output terminal N2b becomes the high level (H). Accordingly, the transmission gate TG2b of the switching circuit 80b is in the ON state, and the low-level electric potential VL is input from the second control line 92 to the pixel electrode 35b.
In addition, a pulse-shaped signal in which a period of the high level (VH) and a period of the low level (VL) are periodically repeated is input to the common electrode 37.
In such a case, an electric potential difference between the pixel electrode 35a and the common electrode 37 is applied to the electrophoretic element 32 during the period in which the common electrode 37 is the low level (VL). Accordingly, as shown in
When the square image P1 is displayed, the first control line 91, the second control line 92, and the common electrode 37 are electrically disconnected from each other by the common power source modulating circuit 64 to be in the high-impedance state. In addition, the pixel electrodes 35 (35a and 35b) to which the voltages are supplied from the first control line 91 and the second control line 92 are also in the high-impedance state. On the other hand, the latch circuits 70 (70a and 70b) are driven, and the input image signals are stored therein.
Image Removing Step
Next, the image removing step S117 will be described. As shown in
Partial Removal Step
First, the partial removal step S115 will be described. The partial removal step S115 is a step for removing the image P1 by driving only the pixel 40 (40A) in which the black display is represented by forming the image P1.
In the partial removal step S115, a low-level electric potential VL is supplied to the first control line 91, and a pulse-shaped signal in which a period of the high level (VH) and a period of the low level (VL) are periodically repeated is input to the common electrode 37. On the other hand, the second control line 92 is in the high impedance state.
As described above, even after the square image P1 is displayed in the image displaying step S101, the image signals input to the pixels 40 (40A and 40B) are stored in the latch circuits 70 (70a and 70b). Accordingly, in the pixel 40 (40A), in which a high-level image signal is input to the latch circuit 70a, for forming the image P1, the transmission gate TG1 (TG1a) is in the ON state. On the other hand, in the pixel 40 (40B), in which a low-level image signal is input to the latch circuit 70b, for forming the background, the transmission gate TG2 (TG2b) is in the ON state.
Accordingly, in the partial removal step S115, the pixel electrode 35 (35a) of the pixel 40 (40A) that forms the image P1 is connected to the first control line 91 and is supplied with the low-level electric potential VL. On the other hand, the pixel electrode 35 (35b) of the pixel 40 (40B) that forms the background is connected to the second control line 92 so as to be in the high-impedance state.
Then, an electric potential difference between the pixel electrode 35 (35a) of the pixel 40 (40A) that forms the image P1 and the common electrode 37 is applied to the electrophoretic element 32 during a period in which the high-level (VH) is supplied to the common electrode 37. Accordingly, the white display is represented by the pixel 40 (40A) that forms the image P1, and the image P1 is removed as shown in
Here, for example, the signal that is input to the common electrode 37 is a pulse, of which the high-level electric potential VH is 15 V, the low-level electric potential VL is 0 V, and the pulse width and the number of the pulses are 20 ms×30 pulses+200 ms×4 pulses. Accordingly, the time interval of application of a voltage for the electrophoretic element 32 is 1.4 s, and a value acquired by multiplying a voltage by the time interval of application of the voltage is 15 V×1.4 s=21 V·s.
On the other hand, the pixel electrode 35 (35b) of the pixel 40 (40B) that forms the background is in the high-impedance state, and the pixel 40 (40B) is not driven in the partial removal step S115. Accordingly, even when a pulse is input to the common electrode 37, there is little influence on the movement of the black particles 26 and the white particles 27, and whereby the white display is maintained in the background. A signal that is the same as the pulse input to the common electrode 37 may be configured to be input to the second control line 92. In such a case, the pixel electrode 35 (35b) of the pixel 40 (40B) that forms the background and the common electrode 37 have a same electric potential, and there is little influence on the movement of the black particles 26 and the white particles 27, and whereby the white display can be maintained in the background.
When the image P1 is removed as described above, the partial removal step S115 is completed.
However, when the image P1 is selectively removed in the partial removal step S115, as shown in
As shown in
Then, when the image P1 is removed in the partial removal step S115, only the raised contour remains so as to be the afterimage P2.
Thus, according to this embodiment, the afterimage P2 is removed in the afterimage removing step S116 described below.
Afterimage Removing Step
The afterimage removing step S116 is a step for removing the afterimage P2. In the afterimage removing step S116, after an afterimage removing area for afterimage removal is set, and the pixels 40 forming the afterimage removing area are driven so as to remove the afterimage P2.
Here, a method of setting the afterimage removing area R2 will be described. The afterimage removing area setting circuit 167 (
Then, the afterimage removing area setting circuit 167 sets an area, which is formed by the pixel 40 (40A) forming the contour and the pixel 40 (40B) that is disposed to be adjacent to the contour so as to form the background, having a width corresponding to two pixels as the afterimage removing area R2. The afterimage P2 is included in the set afterimage removing area R2.
The pixel information that configures the afterimage removing area R2 is output from the afterimage removing area setting circuit 167 to the control circuit 161, and image data D for afterimage removal is generated based on the pixel information by the control circuit 161. The image data D for afterimage removal that is generated by the control circuit 161 is expanded into the frame memory 165, and then is input to the latch circuit 70 of each pixel 40. According to this embodiment, the pixels 40 (40A and 40B) that form the afterimage removing area R2 are extracted from the image data D after being developed into the frame memory 165. However, these pixels 40 (40A and 40B) may be configured to be extracted by analyzing the image data D before expansion by using the control circuit 161. In such a case, the process from extracting the pixels 40 (40A and 40B) that form the afterimage removing area R2 to generation of the image data D for afterimage removal is consistently performed by the control circuit 161.
When the image signal is input to the latch circuit 70, the electric potentials of the high-electric potential power source line 50 and the low-electric potential power source line 49 are set to the electric potentials (VH and VL) for image display.
When the image signals for afterimage removal is input as described above, the transmission gates TG1 (TG1a and TG1b) of the pixels 40 (40A and 40B) to which the high-level (H) image signals are input are in the ON state. On the other hand, the transmission gate TG2 of the pixel 40 to which the low-level (L) image signal is input is in the ON state. In addition, as shown in
The pixel electrodes 35 (35a and 35b) of the pixels 40 (40A and 40B) having the latch circuits 70 to which the high-level (H) image signals are input are connected to the first control line 91 and are supplied with the low-level (VL) electric potential. On the other hand, the pixel electrode 35 of the pixel 40 having the latch circuit 70 to which the low-level (L) image signal is input is connected to the second control line 92 and is in the high-impedance state.
Accordingly, in the pixels 40 (40A and 40B) to which the high-level (H) image signals are input, a voltage corresponding to an electric potential difference between the pixel electrodes 35 (35a and 35b) and the common electrode 37 are applied to the electrophoretic element 32 during a period in which the high-level (VH) electric potential is supplied to the common electrode 37. Accordingly, in the afterimage removing area R2, the black particles 26 move to the pixel electrode 35 side, and the white particles 27 move to the common electrode 37 side, whereby the afterimage P2 is removed.
During a period in which the low-level (VL) electric potential is supplied to the common electrode 37, the pixel electrodes 35 (35a and 35b) and the common electrode 37 have a same electric potential, and accordingly, there is little influence on the movement of the black particles 26 and the white particles 27. On the other hand, in the pixel 40 to which the low-level (L) image signal is input, the pixel electrode 35 is in the high-impedance state. Accordingly, even when a pulse is supplied to the common electrode 37, there is little influence on the movement of the black particles 26 and the white particles 27, and whereby the white display is maintained.
Accordingly, as shown in
In the afterimage removing step S116, the frequency and the number of the pulses input to the common electrode 37 are set such that the balance of the electric potential of the electrophoretic element 32 is maintained over the entire area of the display unit 5 while removing the afterimage P2. The above-described setting of the pulse condition is not for generating unevenness in the displayed image (P1). In addition, under such a pulse condition, there is an advantage that a color change or corrosion of the common electrode 37 can be prevented.
In particular, the pulse condition is set such that a value acquired by multiplying a voltage applied to the electrophoretic element 32 by a time interval of application of the voltage in the afterimage removing step S116 is smaller than a value acquired by multiplying a voltage applied to the electrophoretic element 32 by a time interval of application of the voltage in the partial removal step S115.
Here, for example, the signal that is input to the common electrode 37 in the afterimage removing step S116 is a pulse of which the high-level electric potential (VH) is 15 V, the low-level electric potential (VL) is 0 V, and the pulse width and the number of the pulses are 20 ms×6 pulses. Accordingly, the time interval of application of the voltage for the electrophoretic element 32 is 0.12 s, and the value acquired by multiplying the voltage by the time interval of application of the voltage is 15 V×0.12 s=1.8 V·s. This value is smaller than the value of 21 V·s that is acquired by multiplying the voltage by the time interval of application of the voltage in the partial removal step S115.
When the afterimage P2 is removed, as shown in
Update Image Displaying Step
The update image displaying step S121 is a step for displaying an update image P11 shown in
When the process proceeds to the update image displaying step S121, the image data D for image update is output from the control circuit 161 (
Both the pixels 40A and 40B are pixels 40 that form the update image P11, and accordingly, as shown in
The transmission gates TG1 (TG1a and TG1b) of the pixels 40 (40A and 40B) having the latch circuits 70, to which the high-level (H) image signals are input, are in the ON state. On the other hand, the transmission gate TG2 of the pixel 40 having the latch circuit 70 to which the low-level (L) image signal is input is in the ON state.
When the image signals are input to the latch circuits 70, the electric potentials (Vdd and Vss) of the high-electric potential power source line 50 and the low-electric potential power source line 49 are set to the electric potentials (VH and VL) for image display. Then, as shown in
The pixel electrodes 35 (35a and 35b) of the pixels 40 (40A and 40B) having the latch circuits 70 to which the high-level (H) image signals are input are connected to the first control line 91 and are supplied with the high-level (VH) electric potentials.
On the other hand, the pixel electrode 35 of the pixels 40 having the latch circuit 70 to which the low-level (L) image signal is input is connected to the second control line 92 and is supplied with the low-level (VL) electric potential.
Accordingly, the black display is represented by the pixels 40 (40A and 40B) to which the high-level (H) image signals are input, and the update image P11, shown in
When the rectangular image P11 is displayed, the first control line 91, the second control line 92, and the common electrode 37 are in the high-impedance state, and the update image displaying step S121 is completed. When the image is to be updated consecutively, the image removing step S117 and the update image displaying step S121 are repeatedly performed.
According to the driving method of the third embodiment, the following advantages can be acquired.
First, when the afterimage P2 is removed in the afterimage removing step S116, only the pixels 40 (40A and 40B) that form the afterimage removing area R2 are driven. Accordingly, the afterimage P2 can be removed while suppressing the power consumption. According to this embodiment, the afterimage removing area R2, which is configured by the pixel 40 (40A) that forms the contour and the pixel 40 (40B) that is disposed to be adjacent to the pixel 40 (40A) and forms the background, having a width corresponding to two pixels is set. Accordingly, the number of the pixels driven in the afterimage removing step S116 becomes a minimum. Therefore, the afterimage can be removed while suppressing the power consumption further.
In addition, when the image P1 is removed in the partial removal step S115, an electric potential is supplied to the pixel electrode 35 (35a) of the pixel 40 (40A) that forms the image P1, and the pixel electrode 35 of the pixel 40 that forms the background is in the high-impedance state. Accordingly, the image P1 is selectively removed by driving only the pixel 40 (40A) that forms the image P1. Therefore, the image P1 can be removed while suppressing the power consumption, compared to a case where the previous screen is removed.
In addition, it is preferable that the width of the afterimage removing area R2 is set in accordance with the form of generation of the afterimage that is different depending on the characteristics of the electrophoretic element 32.
For example, the afterimage removing area R2 may be an area that has a width corresponding to three or more pixels by broadening the area to the background side or the image side. In such a case, the number of the pixels to be driven is increased, and the advantage from the viewpoint of the power consumption is degraded. However, in such a case, the pixels 40 in the broader range are driven, and accordingly, generation of the afterimage P2 can be prevented more assuredly. In addition, the afterimage removing area R2 may be an area that is formed of only the pixels located on the background side without including any pixel located on the image side. In such a case, the afterimage removing area R2 can be set as a minimum area that is necessary for removing the afterimage P2, and accordingly, the power consumption can be suppressed.
In addition, by setting a value acquired by multiplying a voltage applied to the electrophoretic element 32 by a time interval of the application of the voltage in the afterimage removing step S116 to be smaller than a value acquired by multiplying a voltage of the pulse applied to the electrophoretic element 32 by a time interval of application of the voltage in the partial removal step S115, the balance of the electric potential of the electrophoretic element 32 is uniformly maintained over the entire area of the display unit 5. Accordingly, generation of unevenness in the displayed image (P1 and P11) and a color change or corrosion of the common electrode 37 can be prevented.
Electronic Apparatus
Next, the cases in which the electrophoretic display device 100, according to each of the above-described embodiments, is applied to an electronic apparatus will be described.
In the front side of the watch case 1002, a display unit 1005 that is configured by the electrophoretic display device 100 according to each of the above-described embodiments, a second hand 1021, a minute hand 1022, and an hour hand 1023 are disposed. In addition, on the side of the watch case 1002, a winder 1010 as an operator, and an operation button 1011 are disposed. The winder 1010 is connected to a hand setting stem (not shown) disposed inside the case and is provided such that the winder, together with the hand setting stem, can be pushed or pulled at multiple levels (for example, two levels) and rotated. In the display unit 1005, an image that becomes the background, a character string such as date, time, or the like, a second hand, a minute hand, an hour hand, and the like can be displayed.
According to the wrist watch 1000, the electronic paper sheet 1100, and the electronic notebook 1200, the electrophoretic display device according to an embodiment of the invention is used as a display unit. Accordingly, an electronic apparatus that can remove an image without generating an afterimage while suppressing the power consumption can be configured.
In addition, the electronic apparatuses shown in
The entire disclosure of Japanese Patent Application Nos. 2008-287713, filed Nov. 10, 2008, 2008-287714, filed Nov. 10, 2008 and 2009-058068, filed Mar. 11, 2009 are expressly incorporated by reference herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2008-287713 | Nov 2008 | JP | national |
| 2008-287714 | Nov 2008 | JP | national |
| 2009-058068 | Mar 2009 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20060209011 | Miyasaka | Sep 2006 | A1 |
| 20070080926 | Zhou et al. | Apr 2007 | A1 |
| 20080238867 | Maeda et al. | Oct 2008 | A1 |
| 20080284768 | Yoshida et al. | Nov 2008 | A1 |
| Number | Date | Country |
|---|---|---|
| 2007-512571 | May 2007 | JP |
| 2007-206267 | Aug 2007 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20100118046 A1 | May 2010 | US |
