Patent Application
20250060983
The architecture of dynamic random access memory (DRAM) is based on a transistor and a capacitor to form a memory cell. One memory cell stores a bit of data in the charged state of the capacitor. However, the capacitor discharges automatically, so an additional circuit must be designed to check the voltage on the capacitors frequently, and charge or discharge frequently to avoid data loss, which is called “memory update”.
In today's applications, DRAM is mainly applied in personal computers, and it can also be applied in graphics cards, scanners, printers, fax machines, image compression and decompression cards, and other electronic devices. However, DRAM has high power consumption. Thus, it is an aim to reduce power consumption of the DRAM.
An embodiment discloses a memory control method for a computing system. The computing system comprises a memory controller, a central processing unit (CPU), and a random access memory (RAM). The memory control method comprises the memory controller determining if the computing system is in low power mode, if the memory controller detects at least one m-channel regions of the RAM has been accessed, the memory controller sending an interrupt to a hypervisor of the CPU, the CPU performing page migration to move data in at least one m-channel region of the RAM to at least one n-channel region of the RAM, where m>n, after completing the page migration, the CPU notifying the memory controller completion of the page migration, and after the CPU notifies the memory controller completion of the page migration, the memory controller can handle the next access event and perform next page migration.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
A lot of power consumption in computing systems and devices comes from dynamic random access memories (DRAMs), and higher computation efficiency comes with higher power consumption. However, it is not always necessary to use a high performance mode for DRAM access in some scenarios. When a high efficiency is not required, a low power mode can be selected to meet the computation demand.
In some embodiments, m-channel DRAM is chosen for the high performance mode to perform high efficiency computation and an n-channel DRAM is chosen for a low power mode to save power consumption where m>n. Thus power modes can be set according to the loading of computations. For example, in a scenario requires lower computation resource, using the m-channel DRAM would cause high power consumption while not improving the performance, thus the n-channel DRAM would be a better choice to save power. The n-channel region and m-channel region in the DRAM can be predetermined and applied by page migration from hypervisor in a central processing unit (CPU). When the low power mode is applied, the operating memory is changed from the m-channel DRAM to n-channel DRAM to save power consumption.
In some embodiments, the RAM 28 is dynamic random access memory (DRAM). The memory controller 24 can record access data in the buffer 25 and determine whether the access event of the application 26 is to be switched from the high performance mode to the low power mode or not when the buffer 25 is full. The way to trigger the interrupt to operate page migration is not only limited to when the buffer 25 is full but also according to other power saving conditions.
In some embodiments, after the hypervisor 23 of the CPU 22 receives the interrupt from the memory controller 24, the hypervisor 23 and MMU 29 read the physical address of the RAM 28 from the buffer 25 and perform the page migration to move the data from the physical address of the RAM 28 to the at least one n-channel region of the RAM 28, where m can be 4, and n can be 2 or 1. In some embodiments, the at least one n-channel region of the RAM 28 is within the at least one m-channel region of the RAM 28. In another embodiment, the at least one n-channel region of the RAM 28 is outside the at least one m-channel region of the RAM 28.
Step 51: the memory controller 24 detects if the access event of the application is to be switched from a high performance mode to a low power mode;
Step 52: the memory controller 24 sends an interrupt to a hypervisor 23 of the CPU 22 if the buffer 25 is full or other power saving conditions are satisfied;
Step 53: the CPU 22 performs page migration to move data in the at least one m-channel region of the RAM 28 to the at least one n-channel region of the RAM 28, where m>n; and
Step 54: the CPU 22 notifies the memory controller 24 completion of the page migration.
In this invention, the low power mode is implemented without changing any hardware. The at least one m-channel region is switched to the at least one n-channel region for reducing power, and most power is saved by using the at least one n-channel region. Whenever the low power mode is desirable, the hypervisor 23 and the MMU 29 of the CPU 22 can save power immediately without hardware changes by performing page migration. Thus, the problem of high power consumption in using DRAM is solved by this invention.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
