The present invention relates to network chips. In particular, the present invention relates to a method of dynamically renumbering ports and an apparatus thereof.
As network chips evolve, the need for handling more and more ports has increased. Adding more ports in a network chip often requires internal parallelism, where a portion of the traffic from each port is handled on a separate pipe. By creating more pipes, more ports can be added without causing the internal frequency of the network chip to be increased. However, increasing the number of ports inside the network chip causes problems in logic where states need to be maintained on a per port basis. For example, if the number of ports on the network chip is 128 and the number of pipes on the network chip is 8, then each pipe handles 16 of the 128 ports. Each of these ports is typically given a unique port number, which allows them to be identified. To represent these ports, an eight bit number is used. The eight bit number can represent a total of 256 ports. State space is 256 entries per pipe to store state information of 16 ports. As such, only a small subset of the state space is used. As the number of ports on a network chip increases, so does the state space per pipe. As the state space per pipe increases, so does the total logic on the network chip. It is inefficient to allocate this much state space since much of the state space is sparse.
Embodiments of the apparatus of dynamically renumbering ports relate to a network chip that minimizes the total logic on the network chip by limiting the number of states that needs to be preserved for all ports on the network chip. Each pipe on the network chip implements a dynamic port renumbering scheme that dynamically assigns a relative port number for each port assigned to that pipe. The dynamic port renumbering scheme allows for internal parallelism without increasing the total amount of state space required for the ports on the network chip.
In one aspect, a method of a network chip is provided. The network chip includes N ports and P pipes. The method includes receiving traffic, and utilizing a dynamic port renumbering scheme by each of the P pipes to renumber each of the N ports associated with that pipe such that hardware implemented on the network chip to preserve state information for the N ports is limited.
In some embodiments, each of the P pipes handles traffic from M ports of the N ports. In some embodiments, each of the P pipes uses M relative port numbers in the dynamic port renumbering scheme. In some embodiments, M is the ceiling of N/P.
In some embodiments, utilizing a dynamic port renumber scheme includes, for each of the P pipes, assigning one of M relative port numbers to each of M ports associated with that pipe, storing all of the assignments of relative port numbers to the M ports, and maintaining all states of the M ports using the M relative port numbers.
In some embodiments, assigning one of M relative port numbers includes determining whether renumbering of one of the M ports is completed, based on the determination that the renumbering of that port is completed, using the relative port number previously assigned to that port, and based on the determination that the renumbering of that port is not completed, assigning an unused relative port number of the M relative port numbers to that port.
In some embodiments, the dynamic port renumbering scheme is a self-learning scheme.
In another aspect, a method of a network chip is provided. The network chip includes N ports and P pipes. The method includes, for each of the P pipes, handling traffic from M ports of the N ports, wherein M is the ceiling of N/P, maintaining no more than state space necessary for the M ports, and assigning one of M relative port numbers to each of the M ports. In some embodiments, the one of the M relative port numbers has not yet been used prior to the assignment.
In some embodiments, assigning one of M relative port numbers to each of the M ports includes receiving traffic, identifying one of the M ports that the traffic is from, and determining whether that port had previously been assigned a relative port number.
In some embodiments, the method also includes based on the determination that that port has not yet been assigned a relative port number, assigning an unused relative port number of the M relative port numbers to that port.
In some embodiments, the method also includes storing all of the assignments of the M relative port numbers to the M ports, and maintaining all states of the M ports using the M relative port numbers.
In yet another aspect, a network chip is provided. The network chip includes N ports and P pipes to handle traffic from the N ports. Each of the P pipes handles traffic from M ports of the N ports. Each of the P pipes uses M relative port numbers in the dynamic port renumbering scheme. Typically, M is the ceiling of N/P.
The network chip also includes a dynamic port renumbering scheme utilized by each of the P pipes to renumber each of the N ports associated with that pipe such that hardware implemented on the network chip to preserve state information for the N ports is limited.
In some embodiments, the dynamic port renumbering scheme, for each of the P pipes, assigns one of M relative port numbers to each of M ports associated with that pipe, stores all of the assignments of relative port numbers to the M ports, and maintains all states of the M ports using the M relative port numbers.
In some embodiments, one of M relative port numbers is assigned based on whether renumbering of one of the M ports that incoming traffic is from is completed. In some embodiments, based on the renumbering of that port being completed, the relative port number previously assigned to that port is used. In some embodiments, based on the renumbering of that port being not completed, an unused relative port number of the M relative port numbers is assigned to that port.
In yet another aspect, a network chip is provided. The network chip includes N ports and P pipes. Each of the P pipes handles traffic from M ports of the N ports, wherein M is the ceiling of N/P, maintains no more than state space necessary for the M ports, and assigns one of M relative port numbers to each of the M ports. In some embodiments, the one of the M relative port numbers has not yet been used prior to the assignment.
In some embodiments, each of the P pipes further receives traffic, identifies one of the M ports that the traffic is from, and determines whether that port had previously been assigned a relative port number.
In some embodiments, based on the determination that that port has not yet been assigned a relative port number, the pipe assigns an unused relative port number of the M relative port numbers to that port.
In some embodiments, each of the P pipes further stores all of the assignments of the M relative port numbers to the M ports and maintains all states of the M ports using the M relative port numbers.
In yet another aspect, a network switch is provided. The network switch includes a plurality of switch ports and at least one network chip. The at least one network chip includes N chip ports and P pipes. Typically, the N chip ports are mapped to the plurality of switch ports. Typically, the P pipes utilize a dynamic port renumbering scheme that learns from previous assignments which relative port number to assign to each of P pipes.
In some embodiments, the dynamic port renumbering scheme is implemented by each of the P pipes.
In some embodiments, each of the P pipes handles traffic from M of the N chip ports, wherein M is the ceiling of M/N.
In some embodiments, each of the P pipes determines whether an incoming port has been assigned a relative port number and based on the determination that the incoming port has not been assigned a relative port number, storing the incoming port in a storage array and assigning the incoming port an unused relative port number based on a current pointer to the storage array.
In some embodiments, the determination is based on whether the incoming port is already stored in the storage array.
The foregoing will be apparent from the following more particular description of example embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the present invention.
In the following description, numerous details are set forth for purposes of explanation. However, one of ordinary skill in the art will realize that the invention can be practiced without the use of these specific details. Thus, the present invention is not intended to be limited to the embodiments shown but is to be accorded the widest scope consistent with the principles and features described herein.
Embodiments of the apparatus of dynamically renumbering ports relate to a network chip that minimizes the total logic on the network chip by limiting the number of states that needs to be preserved for all ports on the network chip. Each pipe on the network chip implements a dynamic port renumbering scheme that dynamically assigns a relative port number for each port assigned to that pipe. The dynamic port renumbering scheme allows for internal parallelism without increasing the total amount of state space required for the ports on the network chip.
Assume N ports are on a network chip and traffic from the N ports are to be handled by P pipes. It is noted that the terms pipes, buses and channels are used interchangeably herein. There is a maximum of M ports assigned to a single pipe, wherein M is the ceiling of N/P (e.g., division is rounded up). For example, if N=128 and P=8, then each pipe handles traffic from no more than 16 ports. For another example, if N=132 and P=8, then each pipe handles traffic from no more than 17 ports.
In the latter example, to represent the 132 ports, an eight bit number is used. The eight bit number can represent a total of 256 ports. However, as explained above, much of the state space of each pipe is unused since only 17 entries are used to maintain 17 port states. Rather than each pipe having state space for all 256 ports, each pipe only needs enough state space for M ports since no more than M ports are assigned to each pipe. To use just enough state space for the ports assigned to a pipe, the dynamic port renumbering scheme renumbers each port assigned to that pipe. Put differently, the dynamic port renumbering scheme dynamically assigns a relative port number to each port assigned to that pipe. These relative port numbers are thereafter used.
In some embodiments, no software is involved (e.g., no programming required). Instead, the dynamic port renumbering scheme is implemented in hardware. In some embodiments, the dynamic port renumber scheme is a self-learning scheme; the dynamic port renumbering scheme learns from previous assignments which relative port number to assign to a port that has not yet been renumbered.
Table 1 shows an exemplary pseudo-code for the dynamic port renumbering scheme.
Referring to
If the ith element of the entries array does not match the incoming port, then i is incremented by one (step 115). While i is less than M where M is the ceiling of N/P (step 120), then the incoming port is continuously checked with other elements of the entries array until the port is found or until i is no longer less than M. If i is no longer less than M, then the port is not found in the entries array (step 125). A port not found in the entries array indicates that the port has not yet been mapped to a relative port number. The port is added to the entries array such that the next time traffic from the same port is received on the pipe, the port will be found in the entries array. In some embodiments, the relative port number assigned to that port is based on a current pointer to the entries array. After the relative port number is assigned, the current pointer is updated. In some embodiments, the current pointer is incremented by one.
At a step 210, a dynamic port renumbering scheme is utilized by each of the P pipes to renumber each of the N ports associated with that pipe such that hardware implemented on the network chip to preserve state information for the N ports is limited. Each of the P pipes uses M relative port numbers in the dynamic port renumbering scheme. In some embodiments, the step 210 includes a method discussed in
At a step 260, based on the determination that the renumbering of that port is completed, the relative port number previously assigned to that port is used.
At a step 265, based on the determination that the renumbering of that port is not completed, an unused relative port number of the M relative port numbers is assigned to that port. In some embodiments, the order of the steps 260 and 265 is not critical. The steps can be performed currently or one before the other.
Returning to
At a step 240, all states of the M ports using the M relative port numbers are maintained.
At a step 310, no more than state space necessary for the M ports are maintained.
At a step 315, one of M relative port numbers is assigned to each of the M ports. The one of the M relative port numbers typically has not yet been used prior to the assignment of the step 315. In some embodiments, the step 315 includes a method discussed in
At a step 335, one of the M ports that the traffic is from is identified.
At a step 340, it is determined whether that port had previously been assigned a relative port number. Based on the determination that that port has not yet been assigned a relative port number, an unused relative port number of the M relative port numbers is assigned to that port.
All of the assignments of the M relative port numbers to the M ports are stored. And, all states of the M ports using the M relative port numbers are maintained.
Typically, the network chip is a part of a network device, such as a network switch, that is able to switch/route network traffic. The network switch includes a plurality of switch ports for receiving packets. The ports on the network chip are typically mapped to the plurality of switch ports. The network traffic is typically handled by the pipes on the network chip. In some embodiments, the network switch includes more than one network chip. The dynamic port renumbering scheme limits the number of states that needs to be preserved for all ports on the network chip, thereby advantageously minimizing the total logic on the network chip.
One of ordinary skill in the art will realize other uses and advantages also exist. While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. Thus, one of ordinary skill in the art will understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.
This Application is a continuation of U.S. application Ser. No. 14/309,789, filed on Jun. 19, 2014, and entitled “A METHOD OF DYNAMICALLY RENUMBERING PORTS AND AN APPARATUS THEREOF,” which is hereby incorporated by reference.
Number | Name | Date | Kind |
---|---|---|---|
5781729 | Baker et al. | Jul 1998 | A |
5805808 | Hasani et al. | Sep 1998 | A |
5951651 | Lakshman | Sep 1999 | A |
6088356 | Hendel et al. | Jul 2000 | A |
6341129 | Schroeder et al. | Jan 2002 | B1 |
6356951 | Gentry | Mar 2002 | B1 |
6606301 | Muller et al. | Aug 2003 | B1 |
6789116 | Sarkissian et al. | Sep 2004 | B1 |
6831917 | Cheriton | Dec 2004 | B1 |
6952425 | Nelson | Oct 2005 | B1 |
7017162 | Smith | Mar 2006 | B2 |
7187694 | Liao | Mar 2007 | B1 |
7293113 | Krishna | Nov 2007 | B1 |
7359403 | Rinne | Apr 2008 | B1 |
7367052 | Desanti | Apr 2008 | B1 |
7391735 | Johnson | Jun 2008 | B2 |
7568047 | Aysan et al. | Jul 2009 | B1 |
7606263 | Parker | Oct 2009 | B1 |
7710959 | Ramasamy et al. | May 2010 | B2 |
7715611 | Eaton et al. | May 2010 | B2 |
7822032 | Parker et al. | Oct 2010 | B1 |
7903689 | Niinomi et al. | Mar 2011 | B2 |
8031640 | Mitsumori | Oct 2011 | B2 |
8054744 | Bishara et al. | Nov 2011 | B1 |
8112800 | Yang et al. | Feb 2012 | B1 |
8144706 | Daniel et al. | Mar 2012 | B1 |
8570713 | Kumfer | Oct 2013 | B2 |
8576713 | Kamerkar | Nov 2013 | B2 |
8705533 | Venkatraman | Apr 2014 | B1 |
8804733 | Safrai | Aug 2014 | B1 |
9064058 | Daniel | Jun 2015 | B2 |
9313115 | Kamerkar | Apr 2016 | B2 |
9525647 | Koponen | Dec 2016 | B2 |
9590820 | Shukla | Mar 2017 | B1 |
9590914 | Alizadeh Attar et al. | Mar 2017 | B2 |
9742694 | Anand | Aug 2017 | B2 |
20010050914 | Akahane et al. | Dec 2001 | A1 |
20020009076 | Engbersen | Jan 2002 | A1 |
20020016852 | Nishihara | Feb 2002 | A1 |
20020062394 | Bunn et al. | May 2002 | A1 |
20020076142 | Song | Jun 2002 | A1 |
20020083210 | Harrison et al. | Jun 2002 | A1 |
20020163935 | Paatela | Nov 2002 | A1 |
20020191521 | Minamino et al. | Dec 2002 | A1 |
20030037154 | Poggio et al. | Feb 2003 | A1 |
20030144993 | Kishigami | Jul 2003 | A1 |
20030152078 | Henderson et al. | Aug 2003 | A1 |
20030193949 | Kojima et al. | Oct 2003 | A1 |
20030198216 | Lewis | Oct 2003 | A1 |
20030210702 | Kendall | Nov 2003 | A1 |
20030218978 | Brown | Nov 2003 | A1 |
20030231625 | Calvignac et al. | Dec 2003 | A1 |
20040019733 | Garinger | Jan 2004 | A1 |
20040064589 | Boucher et al. | Apr 2004 | A1 |
20050076228 | Davis | Apr 2005 | A1 |
20050213570 | Stacy et al. | Sep 2005 | A1 |
20050220107 | DelRegno | Oct 2005 | A1 |
20050232303 | Deforche et al. | Oct 2005 | A1 |
20050246716 | Smith | Nov 2005 | A1 |
20050276230 | Akahane et al. | Dec 2005 | A1 |
20050281281 | Nair et al. | Dec 2005 | A1 |
20060039372 | Sarkinen et al. | Feb 2006 | A1 |
20060168309 | Sikdar et al. | Jul 2006 | A1 |
20060215653 | LaVigne | Sep 2006 | A1 |
20060215695 | Olderdissen | Sep 2006 | A1 |
20060259620 | Tamai | Nov 2006 | A1 |
20060280178 | Miller et al. | Dec 2006 | A1 |
20070078997 | Stern | Apr 2007 | A1 |
20070268931 | Shaikli | Nov 2007 | A1 |
20080008159 | Bourlas et al. | Jan 2008 | A1 |
20090067325 | Baratakke et al. | Mar 2009 | A1 |
20090067446 | Lee | Mar 2009 | A1 |
20090234818 | Lobo et al. | Sep 2009 | A1 |
20090238190 | Cadigan, Jr. et al. | Sep 2009 | A1 |
20090307660 | Srinivasan | Dec 2009 | A1 |
20100161787 | Jones | Jun 2010 | A1 |
20100272125 | Frank et al. | Oct 2010 | A1 |
20100329255 | Singhal | Dec 2010 | A1 |
20110022732 | Hutchison et al. | Jan 2011 | A1 |
20110040923 | Ren | Feb 2011 | A1 |
20110058514 | Lee et al. | Mar 2011 | A1 |
20110134920 | Dyke | Jun 2011 | A1 |
20110142070 | Lim et al. | Jun 2011 | A1 |
20110261698 | Kamerkar | Oct 2011 | A1 |
20110261812 | Kini et al. | Oct 2011 | A1 |
20110268123 | Kopelman et al. | Nov 2011 | A1 |
20110310892 | DiMambro | Dec 2011 | A1 |
20120159132 | Abel | Jun 2012 | A1 |
20120281714 | Chang et al. | Nov 2012 | A1 |
20130039278 | Bouazizi et al. | Feb 2013 | A1 |
20130163427 | Beliveau et al. | Jun 2013 | A1 |
20130163475 | Beliveau et al. | Jun 2013 | A1 |
20130195457 | Levy et al. | Aug 2013 | A1 |
20130215906 | Hidai | Aug 2013 | A1 |
20130238792 | Kind et al. | Sep 2013 | A1 |
20140078902 | Edsall et al. | Mar 2014 | A1 |
20140119231 | Chan et al. | May 2014 | A1 |
20140153443 | Carter | Jun 2014 | A1 |
20140269307 | Banerjee et al. | Sep 2014 | A1 |
20140328354 | Michael | Nov 2014 | A1 |
20140369365 | Denio et al. | Dec 2014 | A1 |
20150081726 | Izenberg | Mar 2015 | A1 |
20150189047 | Naaman et al. | Jul 2015 | A1 |
20150222533 | Birrittella et al. | Aug 2015 | A1 |
20150277911 | Khartikov | Oct 2015 | A1 |
20160274944 | Winkel | Sep 2016 | A1 |
20170048144 | Liu | Feb 2017 | A1 |
Number | Date | Country |
---|---|---|
2000196672 | Jul 2000 | JP |
2000253061 | Sep 2000 | JP |
2003308206 | Oct 2003 | JP |
2005522948 | Jul 2005 | JP |
2007503770 | Feb 2007 | JP |
2007166514 | Jun 2007 | JP |
2009260880 | Nov 2009 | JP |
2009272912 | Nov 2009 | JP |
2013055642 | Mar 2013 | JP |
2014510504 | Apr 2014 | JP |
2005036834 | Apr 2005 | WO |
2011078108 | Jun 2011 | WO |
2012138370 | Oct 2012 | WO |
Entry |
---|
The Office Action and English Translation for the Taiwanese application No. 104111755. |
The Office Action and English Translation for the Taiwanese application No. 104110829. |
Office Action for the Japanese Application No. 2015122564 dated Mar. 25, 2019. |
Office Action for the Japanese Application No. 2015122559 dated Mar. 18, 2019. |
Office Action for the Japanese Application No. 2015122561 dated Mar. 18, 2019. |
Office Action for the Japanese Application No. 2015-122562 dated Mar. 18, 2019. |
The Japanese Office Action dated Mar. 18, 2019, for Japanese Patent Application No. 2015-122560. |
Number | Date | Country | |
---|---|---|---|
20170317951 A1 | Nov 2017 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 14309789 | Jun 2014 | US |
Child | 15653021 | US |