The instant application is a national phase of PCT International Application No. PCT/M2016/001796 filed Oct. 21, 2016, and claims priority to Russian Patent Application Serial No. 2015148643 filed Dec. 11, 2015, the entire specifications of both of which are expressly incorporated herein by reference.
The invention relates to the field of electronic devices for storage of information and can also be applied in processors or other computer devices, telecommunication networks and separate databases.
Leading memory chip production companies such as Samsung and SanDisk have begun to manufacture flash memory of the new generation 3D Vertical NAND (V-NAND), Intel has begun to produce three-dimensional chips with a multilayer three-dimensional structure being a characteristic feature (http://compulenta.computerra.ru/tehnika/microelectronics/10011567/; http://www.cybersercurity.ru/hard/122063.html; www.3dnews.ru/918582).
The known new technology consists in arranging the chips vertically. This makes it possible to obtain the three-dimensional structure of a microchip, hence greatly augment the amount of the stored information and chip elements per unit of area. A serious shortcoming of such multilayer structures consists in a sharp increase, as the quantity of the layers grows, in the density of the electric lines that connect the separate cells and layers with the logical schemes of the switching, which restricts the growth of the quantity of the layers and, consequently, the augmentation of the amounts of memory and the number of the chip elements.
The technical result of the claimed invention consists in simplification of switching the memory cells.
The claimed technical result is achieved through a method for switching the memory cells that consist of memory cell elements formed in a three-dimensional multilayer chip with their electrical connections that go out to the chip facets and with the logical schemes of switching the cells, characterized in that the logical schemes of the switching have been formed on one or several facets of the chip and the schemes communicate with the connection lines that go out to the respective facets of the chip; the memory cells are switched by simultaneously using the logical schemes of the switching and a focused modulated flow of charged particles or electromagnetic radiation that is directed at one or several facets of the chip whereto some electric connection lines go out to and that scans the chip surface according to a preset program to choose a needed memory cell element.
The presented method is implemented as follows.
This invention proposes a method for switching chip cells formed with their mutually perpendicular connection lines in the three-dimensional space so that the connection lines form horizontal rows and columns in each layer and vertical columns that go across all the layers (
Thus, the claimed method makes it possible to avoid augmentation of the density of the electrical connections when increasing the quantity of the layers and considerably simplifies switching the cells of three-dimensional chips.
Number | Date | Country | Kind |
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2015148643 | Dec 2015 | RU | national |
Filing Document | Filing Date | Country | Kind |
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PCT/IB2016/001796 | 10/21/2016 | WO | 00 |
Publishing Document | Publishing Date | Country | Kind |
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WO2017/098319 | 6/15/2017 | WO | A |
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20040120246 | Park | Jun 2004 | A1 |
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20130075844 | Miyano | Mar 2013 | A1 |
20160188495 | Naeimi | Jun 2016 | A1 |
Entry |
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Y. Bai et al., “Study of Multi-level Characteristics for 3D Vertical Resistive Switching Memory,” Jul. 22, 2014, pp. 1-7 [online] [retrieved from https://www.nature.com/articles/srep05780 on Sep. 3, 2018]. |
Detinich, Gennady, “Samsung for about a year sold the SSD to 3D V-NAND at a loss,” Aug. 8, 2015 [online] [retrieved from www.3dnews.ru/918582 on Sep. 3, 2018]. |
Number | Date | Country | |
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20180350435 A1 | Dec 2018 | US |