Claims
- 1. A method of fabricating a semiconductor memory device comprising the steps of:
- forming a MOSFET having a gate electrode, source and drain regions of a second electrical conductivity type impurity material formed in a surface of a semiconductor substrate of a first electrical conductivity type material;
- forming a first inter-layer insulating film over said gate electrode;
- forming a first contact hole such as to expose a surface of said substrate and to be contacted with at least one of the source and drain regions of said MOSFET;
- forming a second contact hole such as to expose a surface of said substrate and to be contacted with another of the source and drain regions of said MOSFET;
- embedding a first electrically conductive layer in said first contact hole up to a position higher than the gate electrode;
- embedding a second electrically conductive layer in said second contact hole up to a position higher than the gate electrode;
- forming a second inter-layer insulating film over said first and second electrically conductive layers;
- forming a third contact hole as a storage node contact hole by selectively removing part of said second inter-layer insulating film to expose the first electrically conductive layer;
- forming a storage node electrode connected to one of the source and drain regions of the MOSFET through said storage node contact hole;
- forming a capacitor insulating film over said storage node electrode;
- forming a plate electrode over said capacitor insulating film;
- forming a third inter-layer insulating film over said plate electrode;
- forming a fourth contact hole as a bit line contact hole by selectively removing part of said second and third inter-layer insulating films to expose the second electrically conductive layer; and
- forming a bit line connected to another of the source and drain regions of said MOSFET through said bit line contact hole.
- 2. A method of fabricating a semiconductor memory device as set forth in claim 1, wherein said first contact forming step includes a step of etching said first inter-layer insulating film so that a sectional area of said first contact hole is larger at portions higher than said gate electrode.
- 3. A method of fabricating a semiconductor memory device as set forth in claim 1 or 2, further comprising a step of etching said first inter-layer insulating film down to a level lower than a top surface of the first embedded electrically conductive layer after the second electrically conductive layer embedding step and prior to the formation of said second inter-layer insulating film.
- 4. A method of fabricating a semiconductor memory device comprising the steps of:
- forming a MOSFET having a gate electrode, source and drain regions of a second electrical conductivity type impurity material formed on a surface of a semiconductor substrate of a first electrical conductivity type material;
- forming a first inter-layer insulating film over said gate electrode;
- forming a first contact hole such as to expose a surface of said substrate and to be contacted with at least one of the source and drain regions of said MOSFET;
- forming a second contact hole such as to expose a surface of said substrate and to be contacted with another of the source and drain regions of said MOSFET;
- embedding a first electrically conductive layer in said first contact hole up to a position higher than the gate electrode;
- embedding a second electrically conductive layer in said first contact hole up to a position higher than the gate electrode;
- forming a second inter-layer insulating film over said first and second electrically conductive layers;
- forming a third contact hole as a bit line contact hole by selectively removing part of said second inter-layer insulating film to expose the first electrically conductive layer;
- forming a bit line connected to one of the source and drain regions of the MOSFET through said bit line contact hole;
- forming a third inter-layer insulating film over said bit line;
- forming a fourth contact hole as a storage node contact hole by selectively removing part of said second and third inter-layer insulating films to expose the second electrically conductive layer;
- forming a storage node electrode connected to another of the source and drain regions of said MOSFET through said storage node contact hole;
- forming a capacitor insulating film over said storage node electrode; and
- forming a plate electrode over said capacitor insulating film.
- 5. A method of fabricating a semiconductor memory device as set forth in claim 4, wherein said first contact forming step includes a step of etching said first inter-layer insulating film so that a sectional area of said first contact hole is larger at portions higher than said gate electrode.
- 6. A method of fabricating a semiconductor memory device as set forth in claim 4 or 5, further comprising a step of etching said first inter-layer insulating film down to a level lower than a top surface of the first embedded electrically conductive layer after the second electrically conductive layer embedding step and prior to the formation of said second inter-layer insulating film.
- 7. A method of fabricating a semiconductor memory device as set forth in claim 6, further comprising a thermal oxidization step of oxidizing a surface of the first embedded electrically conductive layer after said first inter-layer insulating film etching step and prior to the formation of said second inter-layer insulating film.
- 8. A method of fabricating a semiconductor memory device as set forth in claim 4, wherein said first electrically conductive layer embedding step includes a step of forming said first electrically conductive layer thicker than a depth of said first contact hole.
- 9. A method of fabricating a semiconductor memory device as set forth in claim 1 or 2, further comprising a step of etching said first inter-layer insulating film down to a level lower than a top surface of the second embedded electrically conductive layer after the second electrically conductive layer embedding step and prior to the formation of said second inter-layer insulating film.
- 10. A method of fabricating a semiconductor memory device as set forth in claim 4 or 5, further comprising a step of etching said first inter-layer insulating film down to a level lower than a top surface of the second embedded electrically conductive layer after the second electrically conductive layer embedding step and prior to the formation of said second inter-layer insulating film.
- 11. A method of fabricating a semiconductor memory device as set forth in claim 4, further comprising a thermal oxidization step of oxidizing a surface of the first embedded electrically conductive layer after said first inter-layer insulating film etching step and prior to the formation of said second inter-layer insulating film.
- 12. A method of fabricating a semiconductor memory device as set forth in claim 4, wherein said second electrically conductive layer embedding step includes a step of forming said second electrically conductive layer thicker than a depth of said second contact hole.
Priority Claims (2)
Number |
Date |
Country |
Kind |
1-233815 |
Sep 1989 |
JPX |
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2-84372 |
Mar 1990 |
JPX |
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Parent Case Info
This is a division of application Ser. No. 07/578,608, filed Sep. 7, 1990, now U.S. Pat. No. 5,144,579.
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Non-Patent Literature Citations (1)
Entry |
"Dynamic Semiconductor RAM Structures," p. 12, which refers to IBM Technical Bulletin, vol. 15, No. 12, pp. 3585-3586, May 1, 1973. |
Divisions (1)
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Number |
Date |
Country |
Parent |
578608 |
Sep 1990 |
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