Patent Application
20070264780
1. Field of the Invention
The invention, in general, relates to a vertical nano-transistor and, more particularly, to a novel method of its fabrication.
2. The Prior Art
German laid-open patent specification DE-OS 101 42 913 describes a transistor arrangement which resists mechanical stresses caused by bending, shearing or stretching, in which semiconductor material is vertically introduced into micro-holes of a film composite consisting of plastic films with an intermediate metal layer. The semiconductor material is provided with metallic contacts at the upper and lower surfaces of the film composite. However, the application of a metal layer on a plastic film is no easy matter. Moreover, the method of fabricating a vertical transistor arrangement of this type includes a plurality of individual method steps.
The fabrication of a vertical nano-transistor described by US 2002/0001905 is also complex and complicated, since initially a source region is applied to an expensive semiconductor substrate which is not flexible and onto which an insulating layer is applied. Holes in the nm-range are provided in the insulating layer (Al2O3 or Si), and vertically aligned carbon nano-tubes are inserted into these holes. The gate region is arranged above the insulating layer around the carbon nano-tubes and is filled with a non-conductive material up to the upper cover surface of the nano-tubes. Forming the gate region around the nano-tubes and maintaining identical diameters of these nano-tubes during filling has proved to be very difficult, and may result in vertical transistor arrangements which because of the different diameters of the relevant nano-tubes are of different characteristics.
It is, therefore, an object of the invention to provide a novel method of fabricating a vertical nano-transistor capable of resisting mechanical stresses, and which is of lower complexity than what has hitherto been known in the prior art. A memory assembly is to be provided as well.
In accordance with the invention, the object is accomplished by a method of fabricating a vertical nano-transistor provided with a source region, a drain region, a gate region and a semiconductor channel region between the source region and the drain region, wherein the gate region is formed by the steps of embedding the transistor in a metal film such that the gate region and the semiconductor channel region form a coaxial structure and of vertically arranging the source region, the semiconductor channel region and the drain region being arranged and of electrically insulating the gate region from the source region, the drain region and the semiconductor channel region.
In the system in accordance with the invention, the gate region is formed by an extremely thin metal film. The otherwise extremely difficult application of a metal layer onto a plastic film is avoided; also, unlike in the mentioned prior art arrangement, individual films need not be assembled into a composite film. The density of the holes formed in the metal film for providing the coaxial structures is very high.
Embodiments of the invention provide for cylindrically structuring the semiconductor channel region. The diameter of the semiconductor channel region amounts to from several ten to several hundred nanometers. The material of the semiconductor channel region is CuSCN or TiO2 or PbS or ZnO or another compound semiconductor.
The thickness of the metal film forming the vertical gate region is less than 100 μm, preferably 5 to 20 μm. Compared to plastic film, the height of the metal film is more uniform which, given the small thickness, ensures that the inserted holes do indeed penetrate through the film. Moreover, as a result of the very thin metal film, the system according to the invention is highly resistant against mechanical stresses.
In another embodiment the thickness of the electrical insulation in the channel region amounts to several to several hundred nanometers. The thickness of the insulation layer at the upper and lower surfaces of the metal film amounts to several micrometers. The insulation layer may be applied by known processes of thin-film technology.
The material of the source and for the drain regions is Au or Ag or Cu or Ni or Al. The source and drain region may be structured as dots.
The system in accordance with the invention also includes a memory arrangement consisting of a plurality of the inventive vertical nano-transistors arranged adjacent each other on the metal film.
Preferably, the method in accordance with the invention of fabricating the novel vertical nano-transistor consists of, but is not limited to, the steps of forming holes in a thin metal film constituting the gate region of the transistor for providing the channel region, applying a coating of insulating material to the walls of the holes, applying insulating material on the upper and lower surface of the metal film, inserting semi-conductor material into the coated holes for forming the semi-conductor channel region and of applying contacts for forming the source and drain regions.
In preferred embodiments of the method in accordance with the invention the holes in the metal foil are formed by focused ion beams or by laser beams.
The insulating material is applied by thin-film technology or by vacuum filtration of a polymeric solution onto the wall of the holes and onto the upper and lower surface of the metal film.
In other embodiments of the invention the semi-conductor material which may be CuSCN or TiO2 or PbS or ZnO or another compound semi-conductor is introduced into the holes of the metal foil by electro-chemical bath precipitation, by chemical deposition or by the ILGAR process.
The method of fabricating the vertical nano-transistor arrangement in accordance with the invention is simple and adapts to the known thin-film technologies. As a result of the arrangement in accordance with the invention the method of fabrication is no longer limited to predetermined temperatures.
The novel features which are considered to be characteristic of the invention are set forth with particularity in the appended claims. The invention itself, however, in respect of its structure, construction and lay-out, as well as manufacturing techniques, together with other objects and advantages thereof, will be best understood from the following description when read with reference to the drawing.
The drawing depicts the fabrication steps of vertical nano-transistors in accordance with the invention which are embedded in a metal film.
Initially, holes 4 of a diameter of 200 nm are formed by laser irradiation in an Al or Cu film of 30 μm thickness. Thereafter, an insulation layer 2 of organic material, e.g. Al2O3, ZnS, SiO2 or inorganic material, e.g. polystyrene, is applied to the wall of the holes 4 by vacuum filtration of a polymer solution. The thickness of this layer 2 is 50 nm. Thereafter, an insulation layer 2 of a thickness of several micrometers is also applied to the upper and lower surface of the metal film 1 by known thin-film technologies. Following this, the insulated holes 4 in the metal film 1 are filled with CuSCN. This concludes the formation of a semi-conductor channel region 3 of a diameter of 100 nm. As a final step, metallic contacts are applied as drain D and source S contacts.
| Number | Date | Country | Kind |
|---|---|---|---|
| DE 103 39 531.8 | Aug 2003 | DE | national |
The present application is a division of currently pending U.S. patent application Ser. No. 10/568,230 filed 11 Feb. 2006.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10568230 | Feb 2006 | US |
| Child | 11879435 | Jul 2007 | US |
