Patent Application
20120326264
The present invention relates to a method of fabricating a semiconductor device formed of an integrated circuit by electrical connection of a single crystal semiconductor device identified as a circuit element attached on a substrate and a structure identified as a circuit element formed on the substrate, and a semiconductor device fabricated according to the method. More specifically, the present invention relates to a method of fabricating a semiconductor device suitable for usage in a display device such as a liquid crystal display device and an organic electroluminescence display device, and a semiconductor device fabricated according to the method.
In the field of semiconductor devices, the SOI (Silicon On Insulator) technique to form a thin single crystal silicon layer at the surface of an insulation layer is conventionally known. The semiconductor device formed through the SOI technique is directed to reducing the parasitic capacitance and maintaining the insulation resistance at a high level by forming a transistor or the like identified as a circuit element at the aforementioned thin single crystal silicon layer, allowing high performance and large scale integration of the transistor and the like. For the aforementioned insulation layer, a silicon oxide film, for example, is suitable. With regard to a semiconductor device formed through the SOI technique, the thickness of the single crystal silicon layer is preferably made as thin as possible in order to further improve the operation speed and further reduce the parasitic capacitance of the transistor and the like.
The method of enabling the SOI technique includes various methods such as utilizing mechanical polishing, chemical mechanical polishing (CMP), employing porous silicon for the substrate, and the like. As an example of the SOI technique utilizing hydrogen introduction, Bruel proposes a smart cut method including the steps of forming a detachable hydrogen introduction layer by introducing hydrogen into a single crystal semiconductor substrate, attaching the single crystal semiconductor substrate with the formed hydrogen introduction layer to another substrate, applying thermal treatment to detach a portion of the single crystal semiconductor substrate along the hydrogen introduction layer for separation, and transferring the thinned single crystal semiconductor substrate to the additional substrate (refer to Electronics Letters, Vol. 31, No. 14, 1995, p. 1201 (Non-Patent Literature 1), JJAP, Vol. 36, 1997, p. 1636 (Non-Patent Literature 2)).
By a forming a transistor or the like identified as a circuit element at the thinned single crystal semiconductor substrate in such a single crystal semiconductor device formed by the smart cut method, the parasitic capacitance is reduced significantly and the insulation resistance can be maintained at a drastically high level, allowing significant increase in the performance and scale of integration of the transistor and the like.
As a method of transferring a thinned single crystal semiconductor substrate to an additional substrate, there is proposed a method including the steps of forming in advance a flattened hydrophilic oxide film on the face of the single crystal semiconductor substrate and the face of the additional substrate that will be attached to each other, and then attaching the oxide films together, whereby the single crystal semiconductor substrate and additional substrate are attached to each other.
Regarding the approach of transferring a thinned single crystal semiconductor substrate to an additional substrate, application of the relevant technique to fabricate a semiconductor device formed of an integrated circuit by electrically connecting a single crystal semiconductor device identified as a circuit element attached to a substrate and a structure identified as a circuit element formed on the substrate is disclosed in, for example, Japanese Patent Laying-Open No. 2008-66566 (Patent Literature 1) and Japanese Patent Laying-Open No. 2008-147445 (Patent Literature 2).
The publications of Japanese Patent Laying-Open No. 2008-66566 and Japanese Patent Laying-Open No. 2008-147445 disclose a specific method of fabricating a semiconductor device formed of an integrated circuit by electrically connecting a single crystal semiconductor device identified as a circuit element attached to a substrate and a structure identified as a circuit element formed on the substrate, as set forth below.
First, a single crystal semiconductor element such as an MOS (Metal Oxide Semiconductor) transistor is formed on a single crystal semiconductor substrate to obtain a single crystal semiconductor device. Hydrogen is introduced into this single crystal semiconductor device to form a hydrogen-introduced layer at the single crystal semiconductor substrate. The single crystal semiconductor device including the single crystal semiconductor substrate with the hydrogen-introduced layer formed is attached to an additional substrate, followed by thermal treatment, whereby the single crystal semiconductor substrate is detached along the hydrogen-introduced layer to be separated. Accordingly, a single crystal semiconductor device having a thinned single crystal semiconductor substrate is transferred to the aforementioned additional substrate.
Then, the single crystal semiconductor device having wiring and the like formed is attached to a glass substrate. By removing the additional substrate from the single crystal semiconductor device attached to the glass substrate, the single crystal semiconductor device is transferred to the glass substrate. Then, a TFT (Thin Film Transistor) or the like identified as a circuit element is formed on the glass substrate to which is attached the single crystal semiconductor device identified as a circuit element. By electrically connecting the TFT and the like with the MOS transistor and the like provided at the single crystal semiconductor device, an integrated circuit is obtained. Thus, an active matrix type semiconductor device suitable for use in display devices such as a liquid crystal display device and organic electroluminescence display device is formed.
The MOS transistor or the like included in the single crystal semiconductor device set forth above is employed as an active element constituting a microcontroller, a D/A (Digital/Analog) converter, an amplifier, a timing generator, a DSP (Digital Signal Processor), and the like. The TFT or the like formed on the glass substrate is employed as an active element constituting a pixel transistor, a source driver, a gate driver, and the like.
PTL 1: Japanese Patent Laying-Open No. 2008-66566
PTL 2: Japanese Patent Laying-Open No. 2008-147445
Non-Patent Literature 1: Electronics Letters, Vol. 31, No. 14, 1995, p. 1201
Non-Patent Literature 2: JJAP, Vol. 36, 1997, p. 1636
When a single crystal semiconductor device is to be attached to the surface of a glass substrate, the surface roughness of respective attaching faces must be rendered as small as possible such that the glass substrate and the single crystal semiconductor device will be attached with sufficient binding force through van der Waals' force and hydrogen bonding strength. However, an oxide film formed by CVD (Chemical Vapor Deposition) is not suitable for the aforementioned attaching since its as-formed surface roughness is great.
Therefore, the single crystal semiconductor device must have the surface of the oxide film that was obtained by CVD planarized through CMP to achieve a surface roughness suitable for attaching. On part of the glass substrate, it is extremely difficult to planarize the surface of the oxide film formed by CVD by means of CMP since the size of the CMP device currently available is not sufficiently large enough. Accordingly, it is preferable to use the surface of the glass serving as the substrate per se for the attaching face.
Thus, in order to obtain a semiconductor device set forth above, the best condition for attaching is to use the surface of an oxide film planarized by CMP as the attaching face on part of the single crystal semiconductor device and to use the exposed surface of glass itself as the attaching face on part of the glass substrate, and joining these faces together to achieve binding between the single crystal semiconductor device and glass substrate.
Furthermore, in order to obtain the semiconductor device set forth above, accurate positioning of the single crystal semiconductor device on the glass substrate for attaching is indispensable. If this positioning is not performed sufficiently, electrical connection with the circuit elements such as TFT formed on the glass substrate subsequently will become difficult, leading to significant degradation in the yield.
Positioning in the field of semiconductor devices is generally carried out by providing alignment marks at the members that are to be positioned, and setting the position of the members such that the alignment marks overlap each other. In the case where such positioning is to be applied to the semiconductor device set forth above, an alignment mark will be formed in advance at the glass substrate, and another alignment mark will be formed at the single crystal semiconductor device, followed by positioning the glass substrate and the single crystal semiconductor device such that the alignment marks overlap each other.
In consideration of the attaching face of the glass substrate being the surface of the exposed glass per se as mentioned above to ensure the above-described favorable attaching condition, any two of the positioning methods set forth below may be employed.
The first method is directed to forming a recess at the surface of the glass substrate, which will be used as an alignment mark. In the case where this first method is employed, the position of the glass substrate and single crystal semiconductor device is adjusted such that the recess serving as an alignment mark formed in advance at the surface of the glass substrate and the alignment mark formed in advance at the single crystal semiconductor device overlap each other. Thus, positioning of the glass substrate and single crystal semiconductor device is performed.
The second method is directed to forming a film serving as an alignment mark at a portion of the surface of the glass substrate. In the case where the second method is employed, an etching stopped film is provided on the glass substrate to protect the surface. A film constituting an alignment mark and various films for forming a TFT and the like are deposited on the etching stopper film. Then, various films formed on the glass substrate located at the region where a single crystal semiconductor device is to be attached are removed using the etching stopper film. A relevant portion of the etching stopper film is removed to expose an area of the glass substrate surface. Then, the position of the glass substrate and the single crystal semiconductor device is adjusted such that the film remaining on the glass substrate, serving as an alignment mark, and the alignment mark formed in advance at the single crystal semiconductor device overlap each other. Thus, the positioning of the glass substrate and single crystal semiconductor device is performed.
The aforementioned first method is disadvantageous in that a photography step and etching step will be additionally required in order to form a recess serving as an alignment mark at the surface of the glass substrate. The second method is similarly disadvantageous in that a photography step and etching step are additionally required since an etching stopper film is to be formed on the glass substrate, and a portion of the etching stopper film is to be removed subsequently.
Since additional steps to form an alignment mark are required in the event of any of the first and second methods, there will be a problem that the fabrication process is rendered complex and the fabrication cost will be increased. For example, in the case where a TFT of the bottom gate structure is to be formed on the glass substrate, the required number of photolithography steps is appropriately 5 times. In the case where such a TFT is to be formed while employing the first or second method, the required number of photolithography steps will be increased to appropriately 6-7 times. The ratio of increase in the steps and fabrication cost will become extremely high.
The present invention is directed to solving the above-described problems. An object of the present invention is to provide a method of fabricating a semiconductor device formed of an integrated circuit, readily and economically, by electrical connection of a single crystal semiconductor device identified as a circuit element attached on a substrate and a structure identified as a circuit element formed on the substrate. Another object of the present invention is to provide a semiconductor device that can be fabricated readily and economically according to the method of fabricating a semiconductor device.
A method of fabricating a semiconductor device according to the present invention includes the steps of forming a single crystal semiconductor device identified as a circuit element, attaching the single crystal semiconductor device at a predetermined position on a substrate, forming a structure identified as a circuit element differing from the single crystal semiconductor device at a predetermined position on the substrate to which the single crystal semiconductor device is attached, and forming an integrated circuit by electrically connecting the single crystal semiconductor device and the structure identified as circuit elements. In the step of forming a single crystal semiconductor device, an alignment mark is provided at the single crystal semiconductor device. In the step of attaching a single crystal semiconductor device, the single crystal semiconductor device is positioned and attached on the substrate based on mechanical accuracy of an attachment device that attaches the single crystal semiconductor device relative to the substrate. In the step of forming a structure, the structure is positioned and formed on the substrate based on the alignment mark provided at the single crystal semiconductor device.
In the method of fabricating a semiconductor device according to the present invention, the step of forming a single crystal semiconductor device includes the steps of forming a single crystal semiconductor element on one main face of a single crystal semiconductor substrate, thinning the single crystal semiconductor substrate by removing a portion of the single crystal semiconductor substrate from the other main face along the thickness direction, forming an alignment mark at a predetermined position of an exposed face side that has been exposed by thinning the single crystal semiconductor substrate, and forming a planarized film for attaching at the exposed face side of the single crystal semiconductor substrate such that the alignment mark is covered.
In the method of fabricating a semiconductor device according to the present invention, the alignment mark is formed using a portion of a film deposited to form the single crystal semiconductor element at the single crystal semiconductor device.
In the method of fabricating a semiconductor device according to the present invention, the film constituting the alignment mark includes at least one selected from the group consisting of silicon, polysilicon, amorphous silicon, aluminum, molybdenum, tungsten, titanium, titanium nitride, copper, silver, gold and tantalum, as a material.
In the method of fabricating a semiconductor device according to the present invention, the semiconductor included in the single crystal semiconductor device includes at least one selected from the group consisting of a single crystal silicon semiconductor, group IV semiconductor, group II-VI compound semiconductor, group III-V compound semiconductor, group IV-IV compound semiconductor, mixed crystal including a congener element thereof, and oxide semiconductor.
In the method of fabricating a semiconductor device according to the present invention, the substrate is a glass substrate.
In the method of fabricating a semiconductor device according to the present invention, the structure is a TFT.
In the method of fabricating a semiconductor device according to the present invention, the single crystal semiconductor device includes any of an NMOS transistor or a PMOS transistor.
In the method of fabricating a semiconductor device according to the present invention, the single crystal semiconductor device includes an NMOS transistor and a PMOS transistor.
The semiconductor device according to the present invention is fabricated according to any of the above-described methods of fabricating a semiconductor device.
According to the present invention, a semiconductor device formed of an integrated circuit can be fabricated readily and economically by electrical connection of a single crystal semiconductor device identified as a circuit element attached on a substrate and a structure identified as a circuit element formed on the substrate.
An embodiment of the present invention will be described in detail with reference to the drawings. The embodiment will be described based on an example of the present invention applied to an active matrix type semiconductor device suitable for use in a liquid crystal display device, organic electroluminescence display device, and the like. The single crystal semiconductor device that is to be attached will be described based on an example including a CMOS transistor as a single crystal semiconductor element.
In the method of fabricating a semiconductor device according to the present embodiment shown in
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Thus, fabrication of a single crystal semiconductor device including a CMOS transistor with an NMOS transistor and a PMOS transistor as single crystal semiconductor elements is temporarily completed.
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Before describing the attaching process of the single crystal semiconductor device to the additional substrate, a method of forming the additional substrate and its configuration will be described with reference to
In the fabrication of an additional substrate 100 as shown in
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In the attaching process of the single crystal semiconductor device temporarily completed in fabrication to the additional substrate as shown in
Then, in order to improve the binding of the single crystal semiconductor device relative to additional substrate 100, thermal treatment is carried out for approximately two hours at approximately 200° C.-300° C. Accordingly, the attaching process of a single crystal semiconductor device temporarily completed in fabrication to an additional substrate 100 is completed.
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Alignment mark 33A is a positioning mark used in a subsequent step of forming a TFT and the like. Alignment mark 33A is formed at a predetermined position on interlayer insulation film 31 above isolation film 10 where a CMOS transistor, for example, is not formed. This alignment mark 33A has an outer shape of approximately several hundred μm in plan view, considerably large as compared to the size of the CMOS transistor. For the sake of convenience, alignment mark 33A and the CMOS transistor are depicted as having comparable size in the drawings.
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Thus, a method of fabricating a single crystal semiconductor device including a CMOS transistor with an NMOS transistor and a PMOS transistor as single crystal semiconductor elements, and further having an interconnection layer 33 connected to the CMOS transistor and an alignment mark 33A is completed. After fabrication of a single crystal semiconductor device set forth above is completed, the single crystal semiconductor device and additional substrate 100 to which the single crystal semiconductor device is attached are diced into individual pieces, separated as a plurality of dies 35 (refer to
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In order to couple die 35 to glass substrate 36 with favorable binding, the average surface roughness Ra of planarized film 34 and glass substrate 36 is preferably set less than or equal to 0.3 nm (preferably, less than or equal to 0.2 nm). For the purpose of increasing the binding force, die 35 and glass substrate 36 that will be coupled by the van der Waals' force and hydrogen bonding strength is subjected to thermal treatment at approximately 400° C.-600° C. to cause a dehydration reaction (that is, —Si—OH+—Si—OH→—Si—O—Si—+H2) to achieve strong bonding of atoms with each other. In the case where interconnection layer 33 is formed of a metal material of low resistance, this thermal treatment is preferably carried out at a lower temperature. Thus, the attaching process of die 35 including a single crystal semiconductor device with glass substrate 36 is completed.
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In the formation of a TFT, the TFT is positioned in place on glass substrate 36 based on alignment mark 33A provided in the single crystal semiconductor device. More specifically, in the patterning of the above-described various films constituting a TFT, the positioning of the mask for patterning is performed with alignment mark 33A provided in the single crystal semiconductor device as a reference. Thus, a TFT to be formed will be positioned at high accuracy in place on glass substrate 36. Accordingly, the relative position accuracy between the single crystal semiconductor device and the TFT identified as circuit elements will be ensured. Electrical connection of these circuit elements at a subsequent interconnection process can be carried out reliably.
Since only thin insulation films such as interlayer insulation film 31, protection insulation film 30, isolation film 10, and planarized film 26 are present above alignment mark 33A, reading of alignment mark 33A during the formation of a TFT set forth above is allowed through these thin insulation films from the main surface side of glass substrate 36 (i.e. the side to which the semiconductor device is attached). Therefore, alignment mark 33A does not have to be read out from the backside of glass substrate 36 employing a highly transmitting light such as an infrared ray, independent of the thickness of glass substrate 36 or the like, and allowing usage of light of a short wavelength. Thus, positioning can be carried out at high frequency.
In view of the patterning accuracy of each type of film on glass substrate 36 generally being 1 μm-3 μm and the positioning accuracy of attaching the single crystal semiconductor device in the event of using the above-described attachment device being approximately 0.1 μm, the relevant attaching position accuracy is sufficiently smaller than the patterning accuracy. Thus, the TFT alignment above glass substrate 36 is carried out at sufficient high accuracy.
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The characteristic features in the method of fabricating a semiconductor device according to the present embodiment will be summarized in the following. The method of fabricating a semiconductor device according to the present embodiment includes the steps of forming a single crystal semiconductor device identified as a circuit element (refer to
By employing the method of fabricating a semiconductor device according to the present embodiment set forth above, a single crystal semiconductor device is positioned at high accuracy to be attached on glass substrate 36, and a TFT is positioned at high accuracy to be formed on glass substrate 36 relative to the single crystal semiconductor device attached on glass substrate 36. Accordingly, electrical connection of the single crystal semiconductor device with the TFT can be performed reliably, leading to drastic improvement in the yield. Furthermore, by employing the method of fabricating a semiconductor device according to the present embodiment set forth above, it is not required to provide a recess serving as an alignment mark at the main surface of glass substrate 36, or to form a film serving as an alignment mark on the main surface of glass substrate 36. Therefore, the additional photolithography step and etching step are dispensable. The problem of the fabrication step rendered complicated or increased in the fabrication cost will not occur.
By fabricating a semiconductor device based on the method of fabricating a semiconductor device of the present embodiment, a semiconductor device formed of an integrated circuit by electrical connection between a single crystal semiconductor device identified as a circuit element attached on glass substrate 36 and a TFT identified as a circuit element formed on glass substrate 36 can be fabricated readily and economically. As a result, an active matrix type semiconductor device of high performance can be fabricated readily and economically.
Although the present embodiment has been described based on an example in which a single crystal semiconductor device including a CMOS transistor with an NMOS transistor and an PMOS transistor as single crystal semiconductor elements is produced, the single crystal semiconductor element formed in the single crystal semiconductor device may be one of an NMOS transistor and PMOS transistor, or may be another semiconductor device such as a diode or a thyristor bipolar transistor.
The present embodiment has been described based on an example in which a metal film deposited during formation of an interconnection layer is employed as the alignment mark provided at the single crystal semiconductor device. Additionally, instead of a metal film, a film including materials such as silicon, polysilicon, amorphous silicon, aluminum, molybdenum, tungsten, titanium, titanium nitride, copper, sulfur, gold and tantalum may be employed as the alignment mark. Regardless of which material is employed, an additional photolithography step or etching step is not required by forming an alignment mark utilizing a portion of the film deposited for the formation of a single crystal semiconductor element provided at the single crystal semiconductor device. An alignment mark can be formed readily and economically.
The present embodiment has been described based on an example utilizing a silicon substrate as the base material in forming a single crystal semiconductor device. For this base material substrate, a single crystal semiconductor substrate including at least one of a single crystal silicon semiconductor, group IV semiconductor, group II-VI compound semiconductor, group III-V compound semiconductor, group IV-IV compound semiconductor, mixed crystal including a congener element thereof, and oxide semiconductor may be employed.
The present embodiment has been described based on an example utilizing a glass substrate for the substrate to which a single crystal semiconductor device is attached. Additionally, instead of a glass substrate, various types including an insulative substrate such as a plastic substrate, a metal substrate such as of stainless steel covered with a silicon oxide film or/and silicon nitride film can be used. Particularly, in the case where an active matrix type semiconductor device employed an organic electroluminescence display device is to be fabricated, an insulation covered metal plate superior in shock resistance is preferably used since the substrate does not require transparency. In the case where a plastic substrate is employed for the substrate, the single crystal semiconductor device and plastic substrate may be attached by an adhesive or the like.
Although the present embodiment has been described based on an example in which the structure formed on the substrate is a bottom gate structure TFT, a TFT of another structure, or an element other than a TFT, may be the structure formed on the substrate.
Although the present embodiment is described based on an example in which the present invention is applied to an active matrix type semiconductor device suitable for use in a liquid crystal display device or an organic electroluminescence display device, the present invention is applicable to a semiconductor device of other types.
Thus the embodiments disclosed herein are illustrative and non-restrictive in every respect. The technical scope of the present invention is defined by the terms of the claims, and is intended to include any modification within the scope and meaning equivalent to the terms of the appended claims.
1 silicon substrate; 2 thermal oxide film; 3 resist film; 6 thermal oxide film; 7 N well region; 8 P well region; 9 silicon nitride film; 10 isolation film; 11 gate oxide film; 12 gate electrode; 13 resist film; 15 N type low concentration impurity region; 16 resist film; 18 P type low concentration impurity region; 19 sidewall film; 20 resist film; 22 N type high concentration impurity region; 23 resist film; 25 P type high concentration impurity region; 26 planarized film; 28 peel-off substance introduced layer; 29 single crystal silicon thin film; 30 protection insulation film; 31 interlayer insulation film; 32 contact hole; 33 interconnection layer; 33A alignment mark; 34 planarized film; 35 die; 36 glass substrate; 37 underlying insulation film; 38 thin film semiconductor layer; 39 gate insulation film; 40 gate electrode; 41 interlayer insulation film; 42 planarized film; 43 interconnection layer; 100 additional substrate; 101 silicon substrate; 102 thermal oxide film; 103 opening; 104 support; 105 isolation structure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2009-221060 | Sep 2009 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2010/058323 | 5/18/2010 | WO | 00 | 3/23/2012 |
