1. Field of the Invention
The present invention relates to a Schottky barrier diode having an anode and cathode formed on the same plane, and a method of fabricating the Schottky barrier diode.
2. Description of the Related Art
Among conventional methods of fabricating a Schottky barrier diode formed on a semiconductor substrate, there is a method which includes the steps of forming a cathode contact opening region in a silicon oxide film formed on a semiconductor substrate, selectively diffusing or introducing an impurity having the same conductivity type as the semiconductor substrate into the cathode contact opening region by an ion implantation method or the like to form an ohmic contact in a subsequent step, forming an anode contact opening region, forming a metal film on the anode contact opening region to form a Schottky junction, and forming an anode electrode and a cathode electrode (see Japanese Published Patent Application No. H2-178973).
The anode contact opening region and the cathode contact opening region are formed using masks. Therefore, when the two opening regions are positioned a short distance from each other, the anode electrode and the cathode electrode may be shorted due to misalignment of the masks. Thus, it is necessary to provide a given margin between the anode contact opening region and the cathode contact opening region. However, such as margin can be parasitic resistance between the two opening regions, which could result in a decrease in on current of the Schottky barrier diode.
In the case of fabricating a thin film transistor (TFT) and the conventional Schottky barrier diode over the same substrate, there is still a problem of the decrease in on current due to the parasitic resistance of the Schottky barrier diode.
In the above-described method of fabricating the conventional Schottky barrier diode, the anode contact opening region is formed after the formation of the cathode contact opening region and the formation of the diffusion layer in the cathode region. Therefore, the method involves alignment of the cathode contact opening region and the anode contact opening region. In order to suppress the decrease in on current of the Schottky barrier diode due to the parasitic resistance between the two opening regions, it is necessary to form the cathode contact opening region and the anode contact opening region to be as close as possible to each other. However, in that case, it is difficult to obtain sufficient alignment accuracy.
Further, when the positions of the cathode contact opening region and the anode contact opening region vary among Schottky barrier diodes, on currents of the diodes also vary.
Also, when the anode region and the cathode region overlap with each other, off current of the Schottky barrier diode will increase.
In view of the foregoing, it is an object of the invention to fabricate a Schottky barrier diode in which a cathode region and an anode region are positioned as close as possible to each other, variations in position of the anode region and the cathode region are suppressed, a decrease in on current due to parasitic resistance is suppressed, variations in on current are suppressed, and an increase in off current is suppressed.
The invention relates to a Schottky barrier diode, and it is the gist of the invention to form an anode contact opening region in a cathode region, and form an anode region by counter doping.
A method of fabricating a Schottky barrier diode according to one aspect of the invention includes the steps of: forming an island-shape semiconductor film; doping the island-shape semiconductor film with a first impurity element to form a first impurity region; forming an insulating film so as to cover the island-shape semiconductor film; etching the insulating film to form a first opening and a second opening that partly expose the first impurity region; forming a mask over the insulating film so as to cover the first opening and expose the second opening; doping the first impurity region with a second impurity element to form a second impurity region; and forming a first wiring in contact with the first impurity region that is exposed at the first opening, and forming a second wiring in contact with the second impurity region that is exposed at the second opening.
Since the second impurity element is added through the second opening, the periphery of the second opening is also doped with a slight amount of the second impurity element. Therefore, the first impurity region and the second wiring are located away a short distance from each other such that they are not shorted.
According to the invention, a Schottky barrier diode can be fabricated in which a decrease in on characteristics due to parasitic resistance is suppressed and variations in on characteristics are small.
According to the invention, the cathode electrode and the anode region are located a short distance away from each other such that they are not shorted. Therefore, an increase in off current of the Schottky barrier diode can be suppressed.
In the accompanying drawings:
Hereinafter, embodiment modes and embodiments of the invention will be described with reference to the accompanying drawings. Note that the invention can be implemented in various different ways and it will be easily understood by those skilled in the art that various changes and modifications can be made in the invention without departing from the spirit and scope thereof. Therefore, the invention should not be construed as being limited to the description in the following embodiment modes and embodiments.
Each of Embodiment Modes 1 to 3 described below can be freely combined as appropriate unless departing from the spirit and scope of the invention.
Hereinafter, structures of a thin film transistor (TFT) and a Schottky barrier diode, and a method of fabricating them will be described with reference to
First, a base insulating film 112 is formed to a thickness of 30 to 300 nm over a substrate 111 as illustrated in
The base insulating film 112 can have either a single-layer structure or a stacked-layer structure of an insulating film containing oxygen or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiN), silicon oxide containing nitrogen (SiOxNy where x>y; also referred to as silicon oxynitride), or silicon nitride containing oxygen (SiNxOy where x>y; also referred to as silicon nitride oxide). It is particularly preferable to provide the base insulating film when contaminants from the substrate are concerned. In addition, a film having little fixed charge is preferably used for the base insulating film 112. For example, a SiO2 film formed using a mixed gas of SiH4 and N2O can be used.
Next, a semiconductor film is formed to a thickness of 10 to 300 nm. A material of the semiconductor film can be selected in accordance with the characteristics required of a TFT. For example, a semiconductor film such as a silicon film or a silicon germanium film can be used. The semiconductor film is preferably a crystalline semiconductor film formed by depositing an amorphous semiconductor film or a microcrystalline semiconductor film and crystallizing the semiconductor film by a laser crystallization method or the like. Deposition of the microcrystalline semiconductor film can be facilitated by using a SiH4 gas or the like that is diluted with hydrogen or a rare gas element such as fluorine. For the laser, a pulsed laser such as an excimer laser or a continuous-wave laser such as a YVO4 laser can be used.
As a crystallization technique, a rapid thermal annealing (RTA) method using a halogen lamp or a crystallization technique using a heating furnace can be used. Further, it is also possible to use a method which includes the steps of adding a metal element such as nickel to an amorphous semiconductor film and solid-phase growing crystals of the semiconductor film with the added metal as a crystalline nucleus.
Next, the semiconductor film is patterned into island-shape semiconductor films 113a and 113b by photolithography and etching steps. Then, a first insulating film 114 is formed to a thickness of 5 to 50 nm so as to cover the island-shape semiconductor films 113a and 113b. The first insulating film is in contact with the island-shape semiconductor films and functions as a gate insulating film.
The first insulating film 114 can be formed in stacked layers by depositing any of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide containing nitrogen (SiOxNy where x>y), and silicon nitride containing oxygen (SiNxOy where x>y), by a CVD method, a sputtering method, or the like. Alternatively, the first insulating film 114 can be formed in stacked layers by depositing any of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide containing nitrogen (SiOxNy where x>y), and silicon nitride containing oxygen (SiNxOy where x>y), by plasma treatment with high electron density and low electron temperature. In this embodiment mode, the first insulating film 114 is formed with a single layer of a SiOxNy film.
Next, a conductive film 115 to serve as an electrode is formed over the first insulating film 114. The conductive film 115 can be formed using an aluminum (Al) film, a copper (Cu) film, a film containing aluminum or copper as a main component, a chromium (Cr) film, a tantalum (Ta) film, a tantalum nitride film, a titanium (Ti) film, a tungsten (W) film, a tungsten nitride film, a molybdenum (Mo) film, or a stacked film of such films, for example, stacked layers of an Al film and a Ta film, stacked layers of an Al film and a Ti film, or stacked layers of a tungsten nitride film and a W film. In this embodiment mode, the conductive film 115 is formed as a stacked film of tantalum nitride with a thickness of 30 nm and tungsten (W) with a thickness of 370 nm.
Next, a mask 116 is formed over the conductive film 115 by a photolithography technique with the use of a photomask. The mask 116 has a shape that partly overlaps with the island-shape semiconductor film 113a to be a TFT, but does not overlap with the island-shape semiconductor film 113b to be a Schottky barrier diode (
Next, the conductive film 115 is etched using the mask 116, and then the mask 116 is removed. Accordingly, an electrode 117 is formed over the island-shape semiconductor film 113a to be a TFT (
In this embodiment mode, the conductive film 115, which is a stacked film of tantalum nitride of 30 nm thick and tungsten (W) of 370 nm thick, is etched using the mask 116. In the first etching, etching is preferably conducted with high etch selectivity of tungsten relative to tantalum nitride. In the first etching, a mixed gas of SF6, Cl2, and O2 is used for an etching gas, and a mixture ratio of SF6/Cl2/O2 is 33/33/10 seem. Plasma is generated by supplying a power of 2000 W to a coiled electrode at a pressure of 0.67 Pa. In addition, a power of 50 W is supplied to a substrate side (a sample stage), and the temperature of the sample stage is set at +70° C. Next, the second etching is conducted in which tantalum nitride is etched to form the electrode 117. At this time, etching is preferably conducted with high etch selectivity of tantalum nitride relative to the first insulating film 114 so that the first insulating film 114 is hardly etched. In the second etching, plasma is generated by supplying a power of 2000 W to a coiled electrode at a pressure of 0.67 P, and a power of 50 W is supplied to the substrate (the sample stage). Cl2 is used for an etching gas, and the temperature of the sampling stage is set at +70° C.
Dry etching can be used as the etching in this embodiment mode, and an ICP (inductively coupled plasma) etching apparatus may be used.
Next, the island-shape semiconductor films 113a and 113b are doped with a first impurity element. In this embodiment mode, the island-shape semiconductor films 113a and 113b are doped with an impurity that imparts n-type conductivity or p-type conductivity. The impurity that imparts n-type conductivity or p-type conductivity is added to the island-shape semiconductor films 113a and 113b through the first insulating film 114, with the electrode 117 as a mask. Accordingly, impurity regions 118a and 118b that are first impurity regions are formed. The concentration of the impurity element in the first impurity regions 118a and 118b is 1×1019 to 1×1022 atoms/cm3 (preferably, 1×1020 to 5×1021 atoms/cm3). An ion doping method or an ion implantation method may be used as the doping method. For example, in order to impart p-type conductivity to the island-shape semiconductor films 113a and 113b, boron (B), gallium (Ga), or the like can be used as the first impurity element, whereas in order to impart n-type conductivity to the island-shape semiconductor films 113a and 113b, phosphorus (P), arsenic (As), or the like can be used as the first impurity element. In this embodiment mode, in order to form an n-type impurity region in the Schottky barrier diode, the first impurity regions 118a and 118b are doped with phosphorus (P), arsenic (As), or the like that imparts n-type conductivity, as the first impurity element.
Then, an interlayer insulating film 211 is formed. The interlayer insulating film 211 is formed using an organic material or an inorganic material. The interlayer insulating film 211 may have either a single-layer structure or a stacked-layer structure. Openings 212a to 212c are formed in the interlayer insulating film 211 to partly expose the first impurity regions 118a and 118b (
Note that the impurity in the first impurity regions 118a and 118b may be activated before or after the formation of the interlayer insulating film 211. When the interlayer insulating film 211 is a stacked film, the impurity in the first impurity regions 118a and 118b may be activated after the formation of a part of the interlayer insulating film 211. Activation may be conducted by laser irradiation, RTA, thermal treatment using an electric oven, or the like.
Next, a mask 215 is formed. The mask 215 covers the entire region of the TFT whereas it covers a region other than the opening 212c of the Schottky barrier diode (
Next, the first impurity region 118b exposed at the opening 212c is doped with a second impurity element that imparts an opposite conductivity type to the first impurity element which has been added to the first impurity regions 118a and 118b. Accordingly, a second impurity region 216 is formed. In this embodiment mode, boron (B), gallium (Ga), or the like that imparts p-type conductivity is used as the second impurity element added to the second impurity region 216 because phosphorus (P), arsenic (As), or the like that imparts n-type conductivity is used as the first impurity element added to the first impurity regions 118a and 118b. An ion doping method or an ion implantation method may be used as the doping method. Thus, the second impurity element added to the second impurity region 216 is an impurity element that imparts an opposite conductivity type to the first impurity element added to the first impurity regions 118a and 118b. At this time, the second impurity element is added to the extent that the conductivity type of the second impurity region 216 remains unchanged from the conductivity type of the first impurity regions 118a and 118b. The concentration of the second impurity element added to the second impurity region 216 is 1×1018 to 1×1021 atoms/cm3 (preferably, 1×1019 to 5×1020 atoms/cm3).
The second impurity region 216 may also be formed by doping the first impurity region 118b exposed at the opening 212c with the second impurity element in order to prevent activation of the first impurity element that has been added to the first impurity regions 118a and 118b. As the second impurity element added to the second impurity region 216, an inert gas such as He or Ar, or a gas that can be combined with Si such as oxygen or nitrogen can be used. The concentration of the second impurity element added to the second impurity region 216 is 1×1018 to 1×1021 atoms/cm3 preferably, 1×1019 to 5×1020 atoms/cm3). An ion doping method or an ion implantation method may be used as the doping method.
The concentrations of the first impurity element and the second impurity element added to the second impurity region 216, in a region of 30 nm in depth from the surface, are 0.01 to 100 times (preferably, 0.1 to 10 times) as high as those in the surface of the second impurity region 216.
The concentrations of the impurity elements added to the second impurity region 216 are determined so that the second impurity region 216 can have a sheet resistance value of 10 to 100 kΩ/.
Next, wirings 217a to 217d are formed as illustrated in
Next, logical calculation results are shown, which demonstrate the structure in accordance with this embodiment mode can increase the on characteristics of a Schottky barrier diode. Calculation was conducted using TCAD software, Sentaurus (manufactured by Synopsys, Inc.).
The above results show that a Schottky barrier diode fabricated in accordance with this embodiment mode can have a suppressed decreasing rate of on characteristics and, thus, variations in on characteristics can be suppressed.
Hereinafter, structures of a complementary thin film transistor (TFT) and a Schottky barrier diode, and a method of fabricating them will be described with reference to
First, as illustrated in
The base insulating film 412 can have either a single-layer structure or a stacked-layer structure of an insulating film containing oxygen or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide containing nitrogen (SiOxNy where x>y; also referred to as silicon oxynitride), or silicon nitride containing oxygen (SiNxOy where x>y; also referred to as silicon nitride oxide). It is particularly preferable to provide the base insulating film when contaminants from the substrate are concerned. In addition, a film having little fixed charge is preferably used for the base insulating film 412. For example, a SiO2 film formed using a mixed gas of SiH4 and N2O can be used.
Next, a semiconductor film is formed to a thickness of 10 to 300 nm. A material of the semiconductor film can be selected in accordance with the characteristics required of a TFT. For example, a semiconductor film such as a silicon film or a silicon germanium film can be used. The semiconductor film is preferably a crystalline semiconductor film formed by depositing an amorphous semiconductor film or a microcrystalline semiconductor film and crystallizing the semiconductor film by a laser crystallization method or the like. Deposition of the microcrystalline semiconductor film can be facilitated by using a SiH4 gas or the like that is diluted with hydrogen or a rare gas element such as fluorine. For the laser, a pulsed laser such as an excimer laser or a continuous-wave laser such as a YVO4 laser can be used.
As a crystallization technique, a rapid thermal annealing (RTA) method using a halogen lamp or a crystallization technique using a heating furnace can be used. Further, it is also possible to use a method which includes the steps of adding a metal element such as nickel to an amorphous semiconductor film and solid-phase growing crystals of the semiconductor film with the added metal as a crystalline nucleus.
Next, the semiconductor film is patterned into island-shape semiconductor films 413a to 413c by photolithography and etching steps. Then, a first insulating film 414 is formed to a thickness of 5 to 50 nm so as to cover the island-shape semiconductor films 413a to 413c. The first insulating film is in contact with the island-shape semiconductor films and functions as a gate insulating film.
The first insulating film 414 can be formed in stacked layers by depositing any of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide containing nitrogen (SiOxNy where x>y), and silicon nitride containing oxygen (SiNxOy where x>y), by a CVD method, a sputtering method, or the like. Alternatively, the first insulating film 414 can be formed in stacked layers by depositing any of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide containing nitrogen (SiOxNy where x>y), and silicon nitride containing oxygen (SiNxOy where x>y), by plasma treatment with high electron density and low electron temperature. In this embodiment mode, the first insulating film 414 is formed with a single layer of a SiOxNy film.
Next, a conductive film 415 to serve as an electrode is formed over the first insulating film 414. The conductive film 415 can be formed using an aluminum (Al) film, a copper (Cu) film, a film containing aluminum or copper as a main component, a chromium (Cr) film, a tantalum (Ta) film, a tantalum nitride film, a titanium (Ti) film, a tungsten (W) film, a tungsten nitride film, a molybdenum (Mo) film, or a stacked film of such films, for example, stacked layers of an Al film and a Ta film, stacked layers of an Al film and a Ti film, or stacked layers of a tantalum nitride film and a W film. In this embodiment mode, the conductive film 415 is formed as a stacked film of tantalum nitride with a thickness of 30 nm and tungsten (W) with a thickness of 370 nm.
Next, masks 416 are formed over the conductive film 415 by a photolithography technique with the use of photomasks. Each mask 416 has a shape that partly overlaps with the island-shape semiconductor film 413a or 413b to be a TFT, but does not overlap with the island-shape semiconductor film 413c to be a Schottky barrier diode (
Next, the conductive film 415 is etched using the masks 416, and then the masks 416 are removed. Accordingly, electrodes 417a and 417b are formed over the island-shape semiconductor films 413a and 413b to be TFTs (
Next, the island-shape semiconductor films 413a and 413c are doped with a first impurity element. In this embodiment mode, the island-shape semiconductor films 413a and 413c are doped with an impurity that imparts n-type conductivity or p-type conductivity. The first impurity element that imparts n-type conductivity or p-type conductivity is added to the island-shape semiconductor films 413a and 413c through the first insulating film 414, with the electrodes 417a as a mask. Accordingly, first impurity regions 418a and 418c are formed. At the time, a mask is formed over the island-shape semiconductor film 413b in advance to prevent the first impurity element from being added into the island-shape semiconductor film 413b. Then, the mask is removed after the first impurity regions 418a and 418c are formed. The concentration of the impurity element in the first impurity regions 418a and 418c is 1×1019 to 1×1022 atoms/cm3 (preferably, 1×1020 to 5×1021 atoms/cm3). An ion doping method or an ion implantation method may be used as the doping method. For example, in order to impart p-type conductivity to the island-shape semiconductor films 413a and 413c, boron (B), gallium (Ga), or the like can be used as the first impurity element, whereas in order to impart n-type conductivity to the island-shape semiconductor films 413a and 413c, phosphorus (P), arsenic (As), or the like can be used as the first impurity element. In this embodiment mode, in order to form an n-type impurity region in the island-shape semiconductor film 413C to be a Schottky barrier diode, the first impurity regions 418a and 418c are doped with phosphorus (P), arsenic (As), or the like that imparts n-type conductivity, as the first impurity element.
Next, the island-shape semiconductor film 413b is doped with a second impurity element. In this embodiment mode, the island-shape semiconductor film 413b is doped with an impurity that imparts an opposite conductivity type to the impurity which has been added to the island-shape semiconductor films 413a and 413c. The second impurity that imparts n-type conductivity or p-type conductivity is added to the island-shape semiconductor film 413b through the first insulating film 414, with the electrode 417b as a mask. Accordingly, second impurity regions 418b are formed. At the time, a mask is formed over the island-shape semiconductor films 413a and 413c in advance to prevent the second impurity element from being added into the island-shape semiconductor films 413a and 413c. Then, the mask is removed after the second impurity region 418b is formed. The concentration of the impurity element in the second impurity regions 418b is 1×1019 to 1×1022 atoms/cm3 (preferably, 1×1020 to 5×1021 atoms/cm3). An ion doping method or an ion implantation method may be used as the doping method. For example, in order to impart p-type conductivity to the island-shape semiconductor film 413b, boron (B), gallium (Ga), or the like can be used as the second impurity element, whereas in order to impart n-type conductivity to the island-shape semiconductor film 413b, phosphorus (P), arsenic (As), or the like can be used as the second impurity element. In this embodiment mode, boron (B), gallium (Ga), or the like that imparts p-type conductivity is used for the second impurity regions 418b.
Then, an interlayer insulating film 511 is formed. The interlayer insulating film 511 is formed using an organic material or an inorganic material. The interlayer insulating film 511 may have either a single-layer structure or a stacked-layer structure. Openings 512a to 512d are formed in the interlayer insulating film 511 to partly expose the first impurity regions 418a and 418c and the second impurity regions 418b (
Note that the impurities in the first impurity regions 418a and 418c and the second impurity regions 418b may be activated before or after the formation of the interlayer insulating film 511. When the interlayer insulating film 511 is a stacked film, the impurities in the first impurity regions 418a and 418c and the second impurity regions 418b may be activated after the formation of a part of the interlayer insulating film 511. Activation may be conducted by laser irradiation, RTA, thermal treatment using an electric oven, or the like.
Next, a mask 515 is formed. The mask 515 covers the entire region of the TFT whereas it covers a region other than the opening 512c of the Schottky barrier diode (
Next, the first impurity region 418c exposed at the opening 512c is doped with a third impurity element that imparts an opposite conductivity type to the first impurity element which has been added to the first impurity regions 418a and 418c. Accordingly, a third impurity region 516 is formed. In this embodiment mode, boron (B), gallium (Ga), or the like that imparts p-type conductivity is used as the third impurity element added to the third impurity region 516 because phosphorus (P), arsenic (As), or the like that imparts n-type conductivity is used as the first impurity element added to the first impurity regions 418a and 418c. An ion doping method or an ion implantation method may be used as the doping method. Thus, the third impurity element added to the third impurity region 516 is an impurity element that imparts an opposite conductivity type to the first impurity element added to the first impurity regions 418a and 418c. At this time, the third impurity element is added to the extent that the conductivity type of the third impurity region 516 remains unchanged from the conductivity type of the first impurity regions 418a and 418c. The concentration of the third impurity element added to the third impurity region 516 is 1×1018 to 1×1021 atoms/cm3 (preferably, 1×1019 to 5×1020 atoms/cm3).
The third impurity region 516 may also be formed by doping the first impurity region 418c exposed at the opening 512c with the third impurity element in order to prevent activation of the first impurity element that has been added to the first impurity regions 418a and 418c. As the third impurity element added to the third impurity region 516, an inert gas such as He or Ar, or a gas that can be combined with Si, such as oxygen or nitrogen can be used. The concentration of the third impurity element added to the third impurity region 516 is 1×1018 to 1×1021 atoms/cm3 (preferably, 1×1019 to 5×1021 atoms/cm3). An ion doping method or an ion implantation method may be used as the doping method.
The concentrations of the first impurity element and the third impurity element added to the third impurity region 516, in a region of 30 nm in depth from the surface, are 0.01 to 100 times (preferably, 0.1 to 10 times) as high as those in the surface of the third impurity region 516.
The concentrations of the impurity elements added to the third impurity region 516 are determined so that the third impurity region 516 can have a sheet resistance value of 10 to 100 kΩ/.
Next, wirings 517a to 517d are formed as illustrated in
Accordingly, the parasitic resistance of a Schottky barrier diode fabricated in accordance with this embodiment mode is suppressed to the minimum, and the on characteristics of such a Schottky barrier diode are excellent. In addition, the Schottky barrier diode can be formed concurrently with a complementary thin film transistor (TFT).
This embodiment mode will describe a rectifier circuit using a Schottky barrier diode, with reference to
Hereinafter, logical calculation results are shown, which demonstrate that the structures of the Schottky barrier diodes in accordance with Embodiment Modes 1 and 2 can improve the output voltage characteristics of a rectifier circuit. First, a rectifier circuit in
As described above, a rectifier circuit having the Schottky barrier diode with excellent on characteristics, which is fabricated in accordance with Embodiment Mode 1 or 2, can generate high voltage and can perform rectification with high efficiency.
As described above, a semiconductor device fabricated in accordance with the invention can obtain excellent characteristics. Further, when the semiconductor device fabricated in accordance with the invention is applied to various thin film integrated circuits and the like, a higher function and higher added value can be achieved.
This embodiment will describe a semiconductor device that has a rectifier circuit using the Schottky barrier diode of the invention. The semiconductor device in this embodiment is a semiconductor device capable of wireless data transmission.
The antenna section 2001 includes an antenna 2011 that receives external signals and transmits data. The signal transmission method of the semiconductor device can be an electromagnetic coupling method, an electromagnetic induction method, a microwave method, or the like. The transmission method may be selected as appropriate taking an intended use of the device into account, and an antenna that is suitable for the transmission method may be provided.
The power supply section 2002 includes a rectifier circuit 2021 that produces power based on a signal received from the outside through the antenna 2011, a storage capacitor 2022 for storing the produced power, and a constant voltage circuit 2023 for generating a constant voltage to be supplied to each circuit. The rectifier circuit in Embodiment Mode 3 is used for the rectifier circuit 2021.
The logic section 2003 includes a demodulation circuit 2031 that demodulates received signals, a clock generating/compensating circuit 2032 that generates clock signals, a code recognition and determination circuit 2033, a memory controller 2034 that produces a signal for reading data from a memory based on a received signal, a modulation circuit 2035 for modulating an encoded signal to be transmitted, an encoder circuit 2037 that encodes the read data, and a mask ROM 2038 that stores data. Further, the modulation circuit 2035 has a resistor 2036 for modulation.
A code recognized and determined by the code recognition and determination circuit 2033 is a frame termination signal (EOF, End of Frame), a frame starting signal (SOF, Start of Frame), a flag, a command code, a mask length, a mask value, or the like. The code recognition and determination circuit 2033 also has a cyclic redundancy check (CRC) function for detecting transmission errors.
Next, a fabrication process of the semiconductor device capable of wireless data transmission will be described with reference to
As illustrated in
For the substrate 700, a glass substrate made of alumino-borosilicate glass, barium borosilicate glass, quartz, or the like can be used.
The release film 701 is formed by a sputtering method, a plasma CVD method, a coating method, a printing method, or the like using an element such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), or silicon (Si); an alloy material containing such an element as a main component; and/or a compound material containing such an element as a main component, and has a single-layer or a stacked-layer structure. The crystal structure of the release film containing silicon may be any of amorphous, microcrystalline, and polycrystalline.
When the release film 701 has a single-layer structure, it is preferable to form a layer containing tungsten or molybdenum, or a layer containing a mixture of tungsten and molybdenum. Alternatively, a layer containing a tungsten oxide or a tungsten oxynitride, a layer containing a molybdenum oxide or a molybdenum oxynitride, or a layer containing an oxide or an oxynitride of a mixture of tungsten and molybdenum is formed. Note that the mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum.
When the release film 701 has a stacked-layer structure, a layer containing tungsten or molybdenum or a layer containing a mixture of tungsten and molybdenum is preferably formed as a first layer, and a layer containing an oxide, a nitride, an oxynitride, or a nitride oxide of tungsten, molybdenum, or a mixture of tungsten and molybdenum is preferably formed as a second layer.
When the release film 701 is formed as a stacked-layer structure of a layer containing tungsten and a layer containing a tungsten oxide, the release film 701 may be formed by the steps of forming a layer containing tungsten and forming an insulating layer containing an oxide thereon so that the layer containing a tungsten oxide is formed at the interface between the tungsten layer and the insulating layer. Alternatively, the layer containing a tungsten oxide may be formed by processing the surface of the layer containing tungsten by using thermal oxidation treatment, oxygen plasma treatment, N2O plasma treatment, treatment using a solution with strong oxidizing power, such as ozone water, treatment using water to which hydrogen has been added, or the like. This also applies to the case of forming a layer containing a tungsten nitride, a layer containing a tungsten oxynitride, or a layer containing a tungsten nitride oxide. In that case, after forming the layer containing tungsten, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer may be formed on the layer containing tungsten.
A tungsten oxide is represented by WOx, where x satisfies 2≦x≦3. The x may be 2 (WO2), 2.5 (W2O5), 2.75 (W4O11), 3 (WO3), or the like.
Here, the tungsten film is formed by a sputtering method to a thickness of 20 to 100 nm, preferably 40 to 80 nm.
The insulating film 702 can be formed by, for example, generating plasma in the flow of an N2O gas to form a tungsten oxide film on the surface of the release film 701, and then forming a silicon oxide film containing nitrogen by a plasma CVD method.
Next, an insulating film 707 is formed to cover the Schottky barrier diode 703 and the thin film transistor 704. Then, a contact hole is formed in the insulating film 707 to partly expose the conductive film 706 functioning as a source or drain electrode of the thin film transistor 704. A conductive film 708 connected to the conductive film 706 is formed over the insulating film 707.
The insulating film 707 can be formed by the steps of applying polyimide, acrylic, or siloxane polymers and baking them. Alternatively, the insulating film 707 can be formed by a sputtering method, a plasma CVD method, a coating method, a printing method, or the like, using an inorganic compound. The insulating film 707 can have either a single layer or stacked layers. Typical examples of the inorganic compound include silicon oxide, silicon nitride, and silicon oxynitride.
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Note that if the element formation layer 710 can be easily peeled off the substrate 700 without forming the openings 714, the laser irradiation step can be omitted and throughput can be improved.
Next, as illustrated in
In this embodiment mode, since a metal oxide film is formed between the release film 701 and the insulating film 702, the interface between the release film 701 and the insulating film 702 has weak adhesion. Thus, peeling can smoothly proceed at the interface. For this reason, a physical means is used to peel the element formation layer 710 from the substrate 700. However, the invention is not limited thereto. A method can be used, in which a light-transmitting substrate is used as the substrate 700 and an amorphous silicon layer containing hydrogen is used as the release film 701. In such a method, after the step in
Further, after the step in
Further, a method can be used, in which, before attaching the adhesive member 715 to the insulating film 712 in
Next, as illustrated in
Then, the flexible substrate 722 is attached to a UV sheet 731 of a dicing frame 732, as illustrated in
Next, a connection terminal 733 is formed over the conductive film 711, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Here, the conductive film 752a that functions as an antenna is connected to connection terminals of the thin film integrated circuit 772a by conductive particles 754a within the anisotropic conductive adhesive 755a, while the conductive film 752b that functions as an antenna is connected to connection terminals of the thin film integrated circuit 772b by the conductive particles 754b within the anisotropic conductive adhesive 755b.
Then, as illustrated in
Through the above steps, semiconductor devices 762a and 762b that are capable of wireless data transmission can be fabricated as illustrated in
Note that a semiconductor device 764 such as the one illustrated in
Through the steps illustrated in
Next, examples of the application the semiconductor device of this embodiment that is capable of wireless data transmission will be described, with reference to
A semiconductor device 800 of this embodiment may be fixed to an article by being mounted on a printed board, attached to a surface of the article, embedded in the article, and so on. For example, if the product is a book, the semiconductor device may be fixed to the book by being embedded inside paper of the book, and if the product is a package made of an organic resin, the semiconductor device may be fixed to the package by being embedded inside the organic resin. Since the semiconductor device 800 of this embodiment can be compact, thin, lightweight, and flexible, the design quality of the article itself is not degraded even after the device is fixed to the article. Further, by providing bills, coins, securities, bearer bonds, documents, and the like with the semiconductor device 800 of this embodiment, they can be provided with an identification function, and forgery can be prevented by making use of the identification function. Moreover, when the semiconductor device of this embodiment is provided in packaging containers, recording media, personal belongings, food, clothes, daily commodities, electronic appliances, and the like, systems such as inspection systems can be made more efficient.
The present application is based on Japanese Priority Application No. 2006-338012 filed on Dec. 15, 2006 with the Japanese Patent Office, the entire contents of which are hereby incorporated by reference.
Number | Date | Country | Kind |
---|---|---|---|
2006-338012 | Dec 2006 | JP | national |