FIELD OF THE INVENTION
The present invention relates to the field of solar cells; more specifically, it relates to a method of fabricating a solar cell.
BACKGROUND OF THE INVENTION
Solar cells or solar concentrators are semiconductor devices capable of generating electricity using the photovoltaic effect. The relatively high cost of fabricating solar cells has seriously limited the widespread use of solar cells. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove.
SUMMARY OF THE INVENTION
One aspect of the present invention is a method, comprising: creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers.
BRIEF DESCRIPTION OF THE DRAWINGS
The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIGS. 1A through 1J are cross-sectional drawings illustrating fabrication of a solar cell according to embodiments of the present invention;
FIG. 2A is a top view of the solar cell of FIG. 1J;
FIG. 2B is a bottom view of the solar cell of FIG. 1J illustrating a first bus bar geometry and FIG. 2C is an bottom view of the solar cell of FIG. 1J illustrating a second bus bar geometry;
FIG. 3 is a top view of a typical semiconductor substrate having an array of un-singulated solar cell chips fabricated according to the methods illustrated in FIGS. 1A through 1I; and
FIG. 4 is flowchart illustrating integration of solar cell chip fabrication into a semiconductor fabrication facility that also fabricates conventional integrated circuit chips.
DETAILED DESCRIPTION OF THE INVENTION
FIGS. 1A through 1J are cross-sectional drawings illustrating fabrication of a solar cell according to embodiments of the present invention. Generally, integrated circuit chips are fabricated using semiconductor substrates that are thin disc shaped substrates called wafers. The terms substrate and wafer may be used interchangeably herein. An integrated circuit chip is defined as a solid-state device including transistors (e.g., field effect and/or bipolar transistors) forming logic and/or memory circuits. The logic and/or memory circuits may be analog or digital.
In FIG. 1A, a bulk single-crystal silicon substrate 100 has a thickness T1 and a diameter D. In one example, D is about 300 mm and T1 is about 700 microns. In FIG. 1B, substrate 100 of FIG. 1A has optionally been thinned to a thickness T2. In one example T2 is about 300 microns. In one example T2 is less than 700 microns. In one example, T2 is less than about 700 microns and not less than about 300 microns. In one example, substrate 100A is a thinned virgin wafer (i.e., a wafer having had no integrated circuit chip processing) which may be thinned by abrasive grinding (a mechanical process), by chemical-mechanical-polishing (CMP) (which is both a chemical and a mechanical process) or combinations thereof. In one example substrate 1B is formed from a scrap wafer on which conventional integrated circuit chips had been fully or partially fabricated but which either were misprocessed or failed a testing procedure. Thinning may be accomplished by etching (which is a chemical process), by abrasive grinding, by CMP or combinations thereof of either the top, the bottom or both the top and the bottom surfaces of the substrate. In one example substrate 100 (or 100A) are intrinsic or lightly doped P type (e.g., to a resistivity of about 0.5 ohm-cm to about 2.5 ohm-cm). For exemplary purposes, FIGS. 1C through 1J will be illustrated using substrate 100 of FIG. 1A, but it should be understood that the processes described in FIGS. 1C through 1J may be practices on thinned substrate 100A. A method of reclaiming scrap integrated circuit wafers is described in United States Patent Publication US 2008/0014661 by Haag et al. filed on Jul. 11, 2007, which is hereby incorporated by reference.
In FIG. 1C, a P-doped glass layer 108 is applied to a top surface 110 of substrate 100 and a N-doped glass layer 112 applied to a bottom surface 120 of substrate 100. In one example, layers 108 and 112 are applied by spin application of a doped glass suspension followed by a bake to drive out the suspension liquid. In one example, layers 108 and 110 are formed by sputter deposition of boro-silicate and phospho-silicate glasses respectively. After a thermal anneal (e.g., of about 500° C. or higher) the dopants from layers 108 and 112 have diffused into substrate 100 to form a P-doped layer 105 in substrate 100 proximate to top surface 110 and an N-doped layer 115 in substrate 100 proximate to bottom surface 120 as illustrated in FIG. 1D and layers 108 and 112 removed (e.g., by wet etching) resulting in the structure illustrated in FIG. 1D. Alternatively, direct gaseous diffusion may be used to form P-doped layer 105 and N-doped layer 115 by introducing a dopant gas into a furnace at temperatures of about 900° C. or greater.
Alternatively, the process described in FIG. 1C may be eliminated and replaced by a P-type ion implantation (e.g., boron) into top surface 105 and an N-type ion implantation (e.g., phosphorus or arsenic or both) into bottom surface 120 followed by an activation anneal (e.g., of about 800° C. or higher) to form P doped layer 105 and N-doped layer 115 respectively. The ion-implantation process is highly compatible with conventional integrated circuit chip fabrication.
The processes illustrate in FIGS. 1E and 1F are optional. In FIG. 1E, a patterned masking layer 125 having openings 127 is formed on bottom surface 120 of substrate 100. In FIG. 1E, N-doped emitters 130 are formed through N-doped layer 115 into substrate 100 where substrate 100 is not protected by masking layer 125. The N-type dopant concentration of emitters 130 is higher than the N-type dopant concentration of N-doped layer 115.
In a first method, masking layer 125 is a dielectric layer and openings 127 are formed photolithographically. A photolithographic process is one in which a photoresist layer is applied to a surface, the photoresist layer exposed to actinic radiation through a patterned photomask and the exposed photoresist layer developed to form a patterned photoresist layer. After etching openings 127, the photoresist layer is removed and an N-doped glass layer (e.g., phospho-silicate glass) applied (either spun on or sputtered on as described supra for layer 112 of FIG. 1C). After a thermal anneal (e.g., of about 500° C. or higher) the dopant of the glass layer diffuse into substrate 100 forming emitters 130. Masking layer 125 is then removed.
In a second method, masking layer 125 is itself a patterned photoresist layer and an N-type ion implantation (e.g., phosphorus or arsenic or both) into bottom surface 120 followed by an activation anneal (e.g., of about 800° C. or higher) to form emitters 130. The ion-implantation process is highly compatible with conventional integrated circuit chip fabrication. Masking layer 125 is then removed.
For exemplary purposes, FIGS. 1G through 1J will be illustrated with optional emitters 130. In FIG. 1G, an upper passivation layer 135 is formed on top surface 110 and a lower passivation layer 140 is formed on bottom surface 120 of substrate 100. In one example, upper and lower passivation layers comprise silicon dioxide. An antireflective coating 145 is formed on a top surface 150 of upper passivation layer 135.
In FIG. 1H, top contact openings 155 are formed through upper passivation layer 135 and antireflective coating 145 and bottom contact openings 160 are formed through bottom passivation layer 140. Regions of P-doped layer 105 are exposed in openings 155 and emitters 130 (or regions of N-doped layer 115 if optional emitters 130 were not formed) are exposed in openings 160. Openings 155 and 160 may be photolithographically defined and etched prior to removing the patterned photoresist layer of the photolithographic process. Two separate photolithographic/etch processes may be used to form openings 155 and 160 separately. Suitable etch processes include sputter etching, reactive ion etching (RIE) and wet etching.
In FIG. 1I, electrically conductive top metal silicide contacts 165A are formed in P-doped layer where the P-doped layer is not protected by top passivation layer 135 and bottom metal silicide contacts 165B are formed in emitters 130 (or regions of N-doped layer 115 if optional emitters 130 were not formed) where the N-doped layer is not protected by bottom passivation layer 140. Metal silicide contacts 165A and 165B may be formed by blanket deposition of metal layers over top and bottom surfaces 105 and 110 of substrate 100, heating the substrate to about 450° C. or higher to react the metal with silicon forming a metal silicide, and then etching to remove unreacted metal. In one example, metal silicide contacts 165A and 165B comprise palladium silicide or nickel silicide.
In FIG. 1J, an electrically conductive contact frame 170 is formed. Contract frame 170 contacts the entire exposed surface in FIG. 1I of metal silicide contacts 165A. Also an electrically conductive bus bar 175 is formed. Bus bar 175 contacts bottom the entire exposed surface in FIG. 1I of metal silicide contacts 165B. In one example, frame 170 and bus-bar 175 are formed by electrolytic or electroless plating. In electrolytic plating, a thin metal seed layer is blanket deposited, a patterned photoresist layer formed on the seed layer and photoresist layer, metal plated onto the seed layer, the photoresist layer removed and any seed layer not protected by plated metal removed in a flash etch. In one example, the seed deposition process are performed in two separate depositions. The patterned photoresist layers are formed in separate photolithographic processes. In one example, a single plating step may also be used to form both contact frame 170 and bus bar 175.
Alternatively, conventional subtractive etch or damascene wire processes may be used to form contact frame 170 and bus bar 175 in two separate operations. A damascene process is one in which wire trenches or via openings are formed in a dielectric layer, an electrical conductor of sufficient thickness to fill the trenches is deposited on a top surface of the dielectric, and a CMP process is performed to remove excess conductor and make the surface of the conductor co-planar with the surface of the dielectric layer to form damascene wires. In the case of damascene processes, antireflective layer 145 and bottom passivation layer 140 act as polish stops.
FIG. 2A is a top view of the solar cell of FIG. 1J. In FIG. 2A, line 1J-1J indicates the section FIGS. 1A through 1J are illustrations of. In FIG. 2A, contact frame 170 includes a perimeter region 180 proximate to a perimeter 185 of a solar cell chip 190. Contact frame 170 includes integral contact fingers to P-doped region 105 (see FIG. 1J) in openings in top passivation layer 135 antireflective coating 145. Metal silicide contacts 165A (see FIG. 1J) are covered by contact frame 170 which may overlap the perimeter of contacts 165A.
FIG. 2B is a bottom view of the solar cell of FIG. 1J illustrating a first bus bar geometry and FIG. 2C is an bottom view of the solar cell of FIG. 1J illustrating a second bus bar geometry. In FIGS. 2B and 2C, line 1J-1J indicates the section FIGS. 1A through 1J are illustrations of. In FIG. 2B, bus bar 175 includes a bus region 200 proximate an edge 205 of a solar cell chip 190. Bus bar 175 includes integral fingers 210 to emitters 130 (see FIG. 1J) in openings in bottom passivation layer 140. Metal silicide contacts 165B (see FIG. 1J) are covered by bus bar 175 which may overlap the perimeter of contacts 165A. In FIG. 2C, a contact frame 170A comprises a grid of intersecting orthogonal wires 210A and 210B intersecting an optional frame 200A. The structure of FIG. 2C is particularly useful if optional emitters 130 (see FIG. 1F) are not used. Also, if optional emitters 130 (see FIG. 1F) are not used, bus bar 175 may be in the form of an electrically conductive layer or plate that also serves as a backside mirror.
FIG. 3 is a top view of a typical semiconductor substrate having an array of un-singulated solar cells fabricated according to the methods illustrated in FIGS. 1A through 1J. In FIG. 3, an array of solar cell chips 190 are separated by kerfs or streets 215 on substrate 100. Kerfs 215 allow separation or singulation of individual solar cell chips 190. Methods of singulation include mechanical dicing or sawing and laser dicing. Each solar cell chip 190 can range in surface area from about 25 mm2 to about 400 mm2. Though all solar cell chips 190 in FIG. 3 are illustrated as having the same geometric shape (i.e., width and length), solar cell chips having different geometric shapes and thus different surface areas may be fabricated together on the same substrate.
FIG. 4 is flowchart illustrating integration of solar cell chip fabrication into a semiconductor fabricator that also fabricates conventional integrated circuit chips. A process route is a list of processes or fabrication steps a lot of wafers must be processed through in order to fabricate a solar cell or integrated circuit chip. The process route includes, specific tools (or tool types if there is more than one of kind tooling), tool parameter setting (e.g., time, temperature, gas flow. etc) and photolithographic masks. A lot may be a single wafer or more than one wafer. The process route includes the type of substrate to be used. The process route may include a statement of priority in case more than one lot of wafers is waiting in the same queue. For solar cell fabrication, the substrate may be a reclaimed scrap wafer as discussed supra.
In step 225 a solar cell process route is created. This route may include tools used only for conventional integrated circuit (IC) fabrication or a combination of tools used for IC fabrication and tools used only for solar cell (SC) fabrication. In step 230, a lot of solar cell wafers for solar cell manufacture is released to the manufacturing facility. In step 235 the solar cell lot is placed in a tool queue. Generally there is a queue for each tool or group of tools that can perform the process indicated by the route.
In step 240 an integrated circuit chip process route is created. In step 245, a lot of integrated circuit chip wafers for integrated circuit chip manufacture is released to the manufacturing facility. In step 250 the integrated circuit chip lot is placed in a tool queue. The solar cell lot queue of step 235 and the integrated circuit chip queue of step 250 may be the same queue.
From steps 235 and 250 the method proceeds to step 255 where it is determined if the tool for the particular queue has become available. If the tool is not available the method loops back to steps 235 or 250. If in step 255 a tool becomes available, then in step 260 it is determined if an integrated circuit chip lot is waiting for that tool. If there is an integrated circuit chip lot waiting to be processed through the tool, then in step 265, the integrated circuit chip lot is processed through the tool and in step 270 is determined if integrated chip fabrication for that lot is complete. If not, the method loops to step 250 where the integrated circuit chip lot is placed in the queue for the next processing tool on its route.
Returning to step 260, If there is no integrated circuit chip lot waiting, then in step 275, it is determined if a solar cell lot is waiting to be processed through tool. If so, then in step 280 the solar cell lot is processed through the tool and in step 285 is determined if solar cell fabrication for that lot is complete. If not, the method loops to step 235 where the solar cell lot is placed in the queue for the next processing tool on its route.
Returning to step 275, if there is no solar cell lot waiting then the method loops through connector A to step 255. One feature of the flowchart of FIG. 4, is no solar cell lot is run on any tool if there is an integrated circuit chip lot waiting for that tool, so solar cell lots are only run using the excess capacity of the tool (or tool set when there are multiple tools of the same kind.) An adjustment can be made to step 260 to check (if there is an integrated circuit chip lot waiting) if a solar cell lot has been waiting for longer than a target amount of time, in which case the method would go to step 275 instead of 265 even if there is an integrated circuit chip lot waiting for the tool.
Thus the embodiments of the present invention have migrated the costs of fabricating solar cells by using combinations of conventional semiconductor processes, integrating solar cell fabrication into conventional integrated circuit chip fabrication facilities and utilizing scrap integrated circuit chip wafers.
The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.
Patent Application
20100304519
