Patent Application
20070238240
The invention relates to a method of forming a high-voltage field-effect transistor of a memory device such as a non-volatile memory device, particularly a charge-trapping memory device.
Memory cells of a flash memory array are based on trapping of charge carriers in a floating gate or in a dielectric memory layer confined by thin confinement layers, e.g., an ONO-layer sequence. These non-volatile memory cells are electrically programmable and erasable.
The development of flash memory devices comprising such arrays undergoes a continuing decrease in structure sizes. Currently, the NAND-flash technology tends towards structure sizes of 70 nm, whereas the NOR-technology tends towards 90 nm of structure sizes. As a flash memory cell is substantially formed of a field-effect transistor, which comprises the floating gate or ONO-charge-trapping layer adjacent to its gate conductor, memory cell sizes directly scale with the transistor size.
An array of memory cells is generally controlled by logic located in a periphery of the array. This logic also comprises transistors. In the technical field of non-volatile memory, programming or erasing operations with regard to the storage content of memory cells are often performed applying high voltages to those lines (bitlines, wordlines, platelines, etc.) which address respective memory cells. Accordingly, there is a need for high voltage transistors in non-volatile memory, particularly flash memory, but also, e.g., other non-volatile memory types such as FeRAM or MRAM. These voltages may exceed for example 3V.
Such high-voltage transistors particularly deviate from memory cell transistors in that the corresponding diffusion or source/drain regions have a larger lateral extent. The diffusion regions comprise highly doped drain regions (HDD) and lightly doped drain regions (LDD), wherein the LDD regions are placed within the substrate between a channel region of the transistor and the HDD region. The LDD region is provided to reduce the field strength gradient at the pn-junction. As the voltages are higher in the case of high-voltage transistors, the LDD regions must, therefore, be arranged with a larger size as compared with memory cell transistors.
In the case of memory cell transistors, LDD regions are formed, for example, by means of a sidewall spacer technique, according to which an HDD implant is recessed from a respective gate stack. With regard to the high-voltage transistors a former approach was to provide a dedicated photomask which, specifically for the purpose of structuring spacers to protect the LDD region formed underneath, was used to expose a resist and to lithographically structure the layers thereunder in order to form the spacer.
However, this approach has led to asymmetric transistor geometries when structures formed by a first photomask, which defines the gate stack, has some misalignment with the above-mentioned second photomask, which is suited for defining the spacer structures protecting the LDD regions. For example such a misalignment may lead to different properties between the source and drain regions.
To inhibit such alignment issues, a proper biasing would be necessitated in order to secure similar electrical properties of both diffusion regions. Such biasing, however, results in larger design rules with respect to the transistor geometry.
With decreasing structure widths a transition towards forming the LDD spacers as sidewall spacers has thus occurred. Herein, the sidewall spacers are formed at sidewalls of the gate stack by means of depositing an isolating layer (oxide or nitride) of conformal thickness. An anisotropic etching removes horizontal parts of this layer, while vertical parts at the sidewalls are retained. As a result, the width of the LDD region-forming spacer is in scale with the thickness of the conformal layer. An advantage arises from the fact, that no specific photomask needs to be provided in order to define the spacers.
Aspect ratios of a gate stack, on which the conformal layer is deposited, must be kept in a defined range. As structure widths further decrease (towards 90 or 70 nm) the height of the gate stack must also necessarily decrease. As a result thereof, the maximum thickness of the conformal layer also decreases and the lateral extent of a spacer is reduced below a limit, which is necessary to support the reliability of a transistor with regard to field strength gradients.
Therefore, a need arises to retain LDD region-forming spacers of sufficient size, but without necessitating additional photomasks to produce such spacers.
In accordance with one aspect of the invention, there is provided a method of forming a transistor in a charge-trapping memory, comprising: covering a substrate with a gate dielectric layer; depositing a first conductive layer upon the gate dielectric layer; etching the first conductive layer in order to form openings therein, which enclose a first web in the first conductive layer, the first web forming a bottom part of a gate stack of the transistor, the openings being surrounded by further portions of the first conductive layer, which are not removed; implanting the substrate in a region exposed by the openings to form lightly doped drain regions in the substrate adjacent to the gate stack; filling the openings with a spacer material to form each a spacer between the first web and the further portions of the first conductive layer; depositing a second conductive layer upon the first web and the further portions of the first conductive layer and upon the spacer; etching the second and the first conductive layer in order to remove the further portions of the first conductive layer and to form a second web in the second conductive layer, which is located upon the first web, the second web forming an upper part of the gate stack; and implanting the substrate in regions where the further portions have been removed to form highly doped drain regions.
In accordance with another aspect, there is provided a method of forming a high-voltage field-effect transistor in a periphery of a charge-trapping memory cell array, which comprises low-voltage field-effect transistors, comprising: covering a semiconductor substrate with a first conductive layer; forming openings in the first conductive layer by means of lithographic structuring using a first photomask, the openings surrounding a gate web; doping the substrate within the openings to form lightly doped drain regions and forming a spacer in each of the openings by means of filling the opening due to deposition; providing a second photomask in order to remove portions in the first conductive layer selectively with respect to the spacer and with respect to the gate web being protected using the first photomask; and doping the substrate where portions of the first conductive layer have been removed to form highly doped drain regions.
In accordance with a further aspect, there is provided a method of forming a field-effect transistor, comprising: providing a substrate covered with at least a conductive layer; forming a first web in the conductive layer, which represents a bottom part of a gate stack and which is separated from further portions of the conductive layer by means openings; forming lightly doped drain regions within the substrate and below the openings; filling the openings to form spacers therein; selectively removing the further portions of the first conductive layer adjacent to the spacers excluding the web; and forming highly doped drain regions within the substrate in surface regions, where the further portions of the first conductive layer have been removed.
In accordance with a further aspect of the invention, there is provided a field-effect transistor, comprising: a substrate; a gate dielectric layer formed on the substrate; a first gate web formed upon the gate dielectric layer; spacers formed adjacent to and on the both sides of the first gate web; lightly doped drain regions formed in the substrate below the spacers; and highly doped drain regions formed in the substrate adjacent to the lightly doped drain regions, wherein the spacers have a width larger than the width of the first gate web.
According to embodiments, a spacer protecting a lightly doped drain (LDD) region when performing an implant or doping the highly doped drain region is formed by means of lithographic structuring using, e.g., a photomask. The structuring is performed in a conductive layer, which is used to form a bottom part of a gate stack. In order to form the spacers, the openings are filled with spacer material, for example oxide and/or nitride. The spacer material is then planarized. The openings such defined simultaneously enclose the gate web, which is formed by the retained parts of the conductive layer between the openings. Consequently, one and the same photomask is used to define the gate stack and the position of the spacers. No additional photomask is thus necessary to form lightly doped drain regions.
Furthermore, the web and the openings may be provided with structure widths as desired. In particular, the widths of the openings (and thus the LDD forming spacers) may be chosen independently of the size (width or height) of the gate stack.
According to embodiments of the invention, the gate stack comprises at least a bottom and an upper part, wherein the bottom part represents a conductive layer in which the openings are formed that are filled with the spacer material. An upper part (which is not necessarily the uppermost part of conductive portions within the gate stack) is deposited and structured subsequently using a second photomask. As this second photomask merely relates to the memory cell periphery, the structure widths may be provided at a somewhat larger level. In particular, this upper part of the gate stack may have a width larger than that of the bottom part. This may even be necessary as the etching of the diffusion regions (HDD regions) necessitates removing a corresponding second and first conductive layer such that the photomask has to shield the already structured bottom part of the gate stack enclosed between the two spacers.
It is clear to a person skilled in the art and pertaining to the technical field of semiconductor manufacturing, that the aspects and embodiments as detailed herein shall not be limited to the production of high-voltage field-effect transistors. There are many other applications that are known to require large spacers adjacent to a transistor gate. Those other applications and methods of forming the same are considered being included by the scope of the invention.
The invention will become clearer with respect to certain embodiments when taken in conjunction with the accompanying drawings.
For a more complete understanding of the present invention, and the advantages eof, reference is now made to the following descriptions taken in conjunction with the ompanying drawing, in which:
The following list of reference symbols can be used in conjunction with the figures:
The implant dose and the conductivity type of dopants may be chosen as in the conventional case.
Nevertheless, it is also possible that the first conductive layer 6 is made of polysilicon, for example, and the second conductive layer 18 comprises a metal, such as tungsten or a tungsten silicide, or aluminum, etc. In this latter case, two subsequent etch steps may be performed. It is important that the further portions 9 and the material deposited upon the further portions is efficiently removed from the substrate surface.
Substantial components of the transistor 1 are thus formed. Further steps relate to providing a sidewall and/or cap isolation to the gate stack, forming an isolation layer towards a next metal level, and providing contacts 28, 30 to the diffusion regions and the gate stack.
The layout of the transistor geometry is shown in
However, it will become clear that this overlap 32 is not necessary, if conductive layers 6, 18 are of different material, such as polysilicon or tungsten silicide.
It is noted that the substrate area 2 shown in the top view of
