The present application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2007-0102125 (filed on Oct. 10, 2007), which is hereby incorporated by reference in its entirety.
Generally, an isolation layer is formed to discriminate or otherwise define active and inactive areas in a semiconductor device. One method of forming an isolation layer includes shallow trench isolation (STI). In STI, a shallow trench is formed in a semiconductor substrate and is then filled up with an insulating material.
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As semiconductor devices become more highly integrated and downsized, a gap between transistors provided in the semiconductor device is reduced. Accordingly, power used per unit area increases while a width of STI for an isolation layer between the transistors decreases. Therefore, the demand for fine patterning and oxide gap-fill technologies rises. In such a STI forming method, the fine patterning technology is freely applicable to devices up to 65 nm scale using ArF light source. Yet, as semiconductor devices are further reduced in size, a gap of trench to be filled decreases while a depth thereof increases. Therefore, in case of filling the trench with an insulating layer, voids may be generated in the insulating layer.
Embodiments relate to a method of forming an isolation layer in a semiconductor device that prevents void generation in the isolation layer.
Embodiments relate to a method of forming an isolation layer in a semiconductor device which prevents formation of voids in the course of filling a trench with an insulating layer.
Embodiments relate to a method of forming an isolation layer in a semiconductor device that may include at least one of the following steps: sequentially forming an insulating layer and an anti-reflective layer on and/or over a semiconductor substrate; and then forming a photoresist pattern on and/or over the anti-reflective layer; and then forming an insulating layer pattern on and/or over an isolation area by performing an etch process using the photoresist pattern as an etch mask; and then forming a polysilicon layer around the insulating layer pattern.
Embodiments relate to a method of forming an isolation layer in a semiconductor device that may include at least one of the following steps: sequentially forming an insulating layer and an anti-reflective layer over a semiconductor substrate having an isolation area for defining an active region; and then forming a photoresist pattern over the anti-reflective layer; and then forming an insulating layer pattern over the isolation area by performing an etch process using the photoresist pattern as an etch mask; and then forming a polysilicon layer around the insulating layer pattern.
Embodiments relate to a method that may include at least one of the following steps: sequentially forming an insulating layer, an anti-reflective layer and photoresist layer over a semiconductor substrate having an isolation region; and then forming a photoresist pattern corresponding spatially to the isolation region by patterning the photoresist layer; and then forming an insulating layer pattern in the isolation region by performing a first etching process using the photoresist pattern as an etching mask; and then forming a polysilicon layer over the semiconductor substrate to surround the insulating layer pattern such that a portion of the insulating layer pattern protrudes from the uppermost surface of the polysilicon layer.
Embodiments relate to a method that may include at least one of the following steps: sequentially forming an insulating layer and an anti-reflective layer over a semiconductor substrate having an isolation region; and then forming photoresist patterns over the anti-reflective coating layer corresponding spatially to the isolation region; and then forming insulating layer patterns in the isolation region by performing a first etching process using the photoresist patterns as etching masks; and then forming a polysilicon layer over the semiconductor substrate such that the uppermost surface of the polysilicon layer is on a plane spatially below the plane of the uppermost surface of the insulating layer patterns; and then bonding the polysilicon layer to the semiconductor substrate at an interface therebetween.
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Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
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As mentioned herein, a method of forming an isolation layer in a semiconductor device in accordance with embodiments can prevent voids from forming in an isolation layer by filling a trench with an oxide material. Namely, by forming an isolation layer in a manner of depositing polysilicon having stack coverage higher than that of the oxide, it is much less probable that voids may be generated in the course of forming the isolation layer.
An isolation layer is formed in a manner of forming a trench by etching an inactive area portion located on a boundary between an active area and the inactive area and then filling the trench with an insulating layer. Yet, embodiments exclude the trench forming concept. In particular, instead of forming a trench by etching, an insulating layer pattern is formed on and/or over a substrate by etching and such a substance of the substrate as polysilicon is then deposited around the insulating layer pattern. Therefore, the insulating pattern plays a role as a single isolation layer.
Although embodiments have been described herein, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.
Number | Date | Country | Kind |
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10-2007-0102125 | Oct 2007 | KR | national |