BRIEF DESCRIPTION OF THE DRAWINGS
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1
a is a wobble carrier without address information recorded thereon;
FIG. 1
b shows signal SAD and FIG. 1c show shows signal SBC;
FIG. 1
d shows the wobble signal obtained by subtracting the amplified wobble signal of FIG. 1c from the wobble amplified signal of FIG. 1b;
FIG. 2 is a block diagram of a conventional wobble detection circuit detecting ATIP information;
FIG. 3 is a block diagram of a conventional wobble detection circuit detecting ADIP information;
FIG. 4 is a block diagram of a conventional circuit for detecting the wobble carrier frequency;
FIG. 5 is a block diagram of a digital automatic gain controller;
FIG. 6A shows a wobble signal carrying an ADIP synch symbol;
FIG. 6B shows a wobble signal carrying an ADIP data 0 symbol;
FIG. 6C shows a wobble signal carrying an ADIP data 1 symbol;
FIG. 7 shows a conventional process of demodulating a wobble signal carrying ADIP information into ADIP symbols;
FIG. 8 shows pre-pit bits associated with a wobble signal of two successive frames;
FIG. 9 shows four types of permutation patterns of three pre-pit bits making up a pre-pit symbol;
FIG. 10 is a block diagram of a wobble detection circuit according to the invention;
FIG. 11 is a block diagram of a portion of a wobble detection circuit with a sampling rate changed with wobble frequencies according to the invention;
FIG. 12 is a block diagram of a portion of a wobble detection circuit with a 1-bit analog to digital converter according to the invention;
FIG. 13 is a block diagram of an apparatus for detecting the wobble carrier frequency and identifying the optical disk format according to the invention;
FIG. 14 is a block diagram of an apparatus for detecting the wobble carrier frequency of an optical disk according to the invention;
FIG. 15
a shows a wobble signal before the filtration of an adjustable band pass filter;
FIG. 15
b shows the signal after the filtration of the adjustable band pass filter;
FIG. 15
c shows the envelope of the signal of FIG. 15b;
FIG. 16 is a block diagram of an apparatus for identifying the optical disk format according to the invention;
FIG. 17 is a flowchart of a method for detecting the wobble carrier frequency of an optical disk according to the invention;
FIG. 18 is a block diagram of a wobble detection circuit according to the invention;
FIG. 19 is a block diagram of a digital automatic gain controller according to the invention;
FIG. 20 is a detailed block diagram of a digital automatic gain controller with low sampling rate according to the invention;
FIG. 21
a shows an amplified signal;
FIG. 21
b shows a digital envelope signal derived from the amplified signal of FIG. 21a by an envelope detection module and a ADC of FIG. 20;
FIG. 21
c shows a difference signal corresponding to the digital envelope signal of FIG. 21b;
FIG. 21
d shows a digital gain signal derived from the difference signal of FIG. 21c by a digital control module of FIG. 20;
FIG. 22 is another detailed block diagram of a digital automatic gain controller with low sampling rate according to the invention;
FIG. 23
a shows an amplified signal;
FIG. 23
b shows an envelope magnitude derived from the amplified signal of FIG. 23a by an envelope detection module of FIG. 22;
FIG. 23
c shows a digital envelope signal corresponding to the envelope magnitude of FIG. 23b;
FIG. 23
d shows a difference signal corresponding to the digital envelope signal of FIG. 23c;
FIG. 23
e shows a digital gain signal derived from the difference signal of FIG. 23d by a digital control module of FIG. 22;
FIG. 24 is a detailed block diagram of a digital automatic gain controller with low signal resolution and high sampling rate according to the invention;
FIG. 25
a shows an amplified signal;
FIG. 25
b shows an envelope magnitude derived from the amplified signal of FIG. 25a by a rectifier module of FIG. 24;
FIG. 25
c shows a 1-bit difference data stream corresponding to the envelope magnitude of FIG. 25b;
FIG. 25
d shows a digital gain signal derived from the difference signal of FIG. 25c by a digital control module of FIG. 24.
FIG. 26 is a block diagram of an apparatus for demodulating ADIP symbols according to the invention;
FIG. 27 shows signal processing of demodulating a wobble signal carrying ADIP information into ADIP symbols according to the invention;
FIG. 28 is a block diagram of a waveform difference measurement module according to the invention;
FIG. 29 is a block diagram of a pattern matching module according to the invention;
FIG. 30 is a flowchart of a method for demodulating ADIP symbols according to the invention;
FIG. 31 is a block diagram of an apparatus for demodulate ADIP symbols of HD-DVD disks according to the invention;
FIG. 32 is a block diagram of the apparatus for demodulating pre-pit symbols according to the invention;
FIG. 33
a shows signal SAD and FIG. 33b show shows signal SBC;
FIG. 33
c shows a wobble peak signal drives by a peak detection unit of FIG. 34;
FIG. 33
d shows a blank detection signal;
FIG. 34 is an exemplary block diagram of an apparatus for detecting the blank sector on an optical disk using the wobble signals; and
FIG. 35 is a flow chart of the blank detection method.
DETAILED DESCRIPTION OF THE INVENTION
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
FIG. 10 is an exemplary block diagram of a wobble detection circuit 1000 according to the invention. A pickup head detects four reflection signals SA, SB, SC, and SD reflected from an optical disk, wherein signals SA, SD and signals SB, SC are respectively representing light intensity reflected from the opposite sides of a track. The reflection signals SA and SD are then added to obtain a signal SAD0, and the reflection signals SB and SC are then added to obtain a signal SBC0. Because the signals SAD0 and SBC0 comprise high frequency noise induced by radio frequency signals and low frequency noise induced by servo signals, low pass filters 1002 and 1012 and high pass filters 1004 and 1014 respectively eliminate the high frequency noise and the low frequency noise from the signals SAD0 and SBC0, and signals SAD2 and SBC2 are obtained.
Two automatic gain controllers (AGC) 1006 and 1016 then amplify the signals SAD2 and SBC2 to the same signal level to obtain signals SAD3 and SBC3. An adder 1020 then subtracts the signal SBC3 from the signal SAD3 to obtain a wobble signal W0. The more balanced the signals SBC3 and SAD3, the less radio frequency noise remains in the wobble signal W0. To minimize aliasing of the wobble signal W0, an anti alias filter (AAF) 1022 then filters off aliasing components of the wobble signal W0 to obtain a wobble signal W1. After the wobble signal W1 passes a high pass filter 1024 to obtain a wobble signal W2, an analog to digital converter 1026 converts the analog wobble signal W2 to a digital wobble signal D1.
The ATIP information carried by the digital wobble signal D1 is modulated within a frequency range. To extract the ATIP information, a digital band pass filter 1030 accepts frequency components of the digital wobble signal D1 within a pass band and rejects frequency components of the digital wobble signal D1 outside the pass band to obtain a digital wobble signal D2. An ATIP detector 1032 then extracts ATIP information from the digital wobble signal D2. A wobble phase locked loop 1034 also locks the phase of the digital wobble signal D2 to generate a clock signal [not shown] with the same frequency as the digital wobble signal D2. Additionally, an address in pre-groove (ADIP) detector 1028 derives ADIP information from the wobble signal D1.
Because the analog to digital converter 1026 converts the analog wobble signal W2 to the digital wobble signal D1, the band pass filter 1030 can digitally filter the digital wobble signal D1 to generate the digital filtered wobble signal D2. Digital signal filtration has an advantage of signal processing simplicity over analog signal filtration. Samples of a digital signal are taken as a series of variables of a filter function, and a digital filter calculates the outputs of the filter function with the input variables of digital signal samples to obtain samples of a filtered signal. Analog filtration, however, requires analog circuits with complicated circuit design and numerous circuit components such as resistors and capacitors to complete analog filtration. Additionally, an analog filter requires high current to drive the circuit components thereof, consuming considerable energy. Thus, the wobble detection circuit 1000 with the digital band pass filter 1030 has simpler circuit design, lower hardware cost, and reduced energy consumption compared with conventional wobble detection circuits.
FIG. 11 is an exemplary block diagram of a portion of a wobble detection circuit 1100 with a sampling rate changed with wobble frequencies according to the invention. An optical disk drive reads optical disk of multiple categories. Because center frequencies of wobble signals of different optical disk types are also different, if an analog to digital converter 1106 converts a wobble signal W2 to a digital wobble signal D1 with a constant sampling rate, the center frequency of band pass filter or other filter will not changed according to wobble signal carrier frequency.
Accordingly, the analog to digital converter 1106 samples the analog wobble signal W2 according to trigger of a clock signal [not shown] with the wobble frequency of the analog wobble signal W2. Thus, the sampling rate of the analog to digital converter 1106 changes with the wobble frequency. In one embodiment, the clock signal triggering the analog to digital converter 1106 is generated by the phase locked loop 1114. In another embodiment, because the wobble frequency of an optical disk spun with constant angular velocity can be estimated according to address information of the analog wobble signal W2, the clock signal is generated according to the address information, and the sampling frequency of the analog to digital converter 1106 is changed with the address information.
FIG. 12 is an exemplary block diagram of a portion of a wobble detection circuit 1200 with a 1-bit analog to digital converter 1206 according to the invention. To ensure that the filtered wobble signal D2 is of good filtration quality, the analog to digital converter 1206 samples the analog wobble signal W2 with high sampling frequency. To simplify the filtration process of the digital band pass filter 1210, signal resolution of the digital wobble signal D1 input thereto is lowered. In one embodiment, the analog to digital converter 1206 is a 1-bit analog to digital converter, a decision maker or a comparator, converting the analog wobble signal W2 to a digital wobble signal D1 of 1-bit data stream. When the analog to digital converter 1206 is a 1-bit analog to digital converter, the sampling frequency is about exceeding eight times the wobble carrier frequency.
The invention provides a wobble detection circuit with a digital band pass filter. Unlike analog band pass filters, the digital band pass filter does not require complicated circuit design occupying large chip area and high current to drive circuit components thereof, thus, reducing chip size of the wobble detection circuit and decreasing energy consumption thereof.
Please refers to FIG. 13, FIG. 13 is an exemplary block diagram of an apparatus 1300 for detecting the wobble carrier frequency and identifying the optical disk format according to the invention. Apparatus 1300 includes a push-pull processor 1302, generating the wobble signal shown in FIG. 1d, and a frequency detection and disk format identification module 1304, detecting the wobble carrier frequency and the disk format of the optical disk. The frequency detection and disk format identification module 1304 adopts a new architecture and method different from the conventional circuit 400 to detect the wobble carrier frequency and identify the optical disk type. In the novel architecture and method provided by the invention, remnant noise existing in the wobble signal generated by push-pull processor 1302 does not affect the detection of the wobble carrier frequency in frequency detection and disk format identification module 1304.
First, as mentioned above the reflected signals SA, SB, SC, SD are simultaneously obtained by scanning a track of the optical disk. And synthesized signal SAD and SBC as shown in FIGS. 1b and 1c are obtained accordingly. The push-pull processor 1302 then processes the signals SAD and SBC to generate the wobble signal S1 as shown in FIG. 13. The push-pull processor 1302 includes two low pass filters 1312 and 1322, two high pass filters 1314 and 1324, two automatic gain controllers 1316 and 1326, and a adder 1330. The low pass filters 1312 and 1322 first respectively exclude the high-frequency noise of the signals SAD and SBC. The high pass filters 1314 and 1324 then respectively exclude the low-frequency noise of the signals SAD and SBC. After filtration, the filtered signals SAD and SBC are further amplified to an appropriate strength level by the automatic gain controllers 1316 and 1326 for further processing, so that the amplified signals meet the same strength level. The more equivalent the strength level of the amplified signals SAD and SBC, the less the remnant noise existing in the output signal of the push-pull processor 1302. The adder 1330 then subtracts the amplified signal SBC from the amplified signal SAD to obtain the signal S1.
The frequency detection and disk format identification module 1304 then detects the wobble carrier frequency of the optical disk according to signal S1. Because each format of optical disk has a distinctive wobble carrier frequency, the optical disk format is identified if the wobble carrier frequency is determined. The frequency detection and disk format identification module 1304 includes an anti-alias filter 1332, an offset canceller 1334, a binary conversion module 1336, an adjustable band pass filter 1342, a frequency detection module 1344, and a disk format identification module 1346. The frequency detection and disk format identification module 1304 is further described in the following with FIGS. 14˜16.
FIG. 14 is a block diagram of an apparatus 1400 for detecting the wobble carrier frequency of an optical disk according to the invention. The apparatus 1400 is a sub-module of the frequency detection and disk format identification module 1304 and includes the anti-alias filter 1332, the offset canceller 1334, the binary conversion module 1336, the adjustable band pass filter 1342, and the frequency detection module 1344. The anti-alias filter 1332 restricts the bandwidth of the signal S1 to obtain a signal S2 approximately satisfying the Shannon-Nyquist sampling theorem. In one embodiment, the anti-alias filter 1332 is a low pass filter. Before the filtered signal S2 being converted from analog-to-digital via binary conversion module 1336, the direct current offset of the signal S2 is cancelled in advance by the offset canceller 1334 to obtain a signal S3. In one embodiment, the offset canceller 1334 is a high pass filter. The binary conversion module 1336 then converts the analog wobble signal S3 to a binary data stream S4. In one embodiment, the binary conversion module 1336 is a comparator.
The adjustable band pass filter 1342 then filters the binary data stream S4 according to an adjustable frequency range, the center frequency of which is sequentially adjusted according to a frequency selection signal. FIG. 15a shows the wobble signal S3 before the filtration of the adjustable band pass filter 1342. The frequency selection signal may direct the adjustable band pass filter 1342 to sequentially filter the binary data stream S4 with multiple predetermined frequency ranges, the union of which overlaps a potential range of the wobble carrier frequency. For example, seven predetermined frequency ranges are applied to filter the data stream S4, and the center frequency of the predetermined frequency ranges are fs1˜fs7. Only the adjustable frequency range of the binary data stream is passed by the adjustable band pass filter 1342 to generate a filtered signal S5. An example of the signal S5 after filtration is shown in FIG. 15b. Because the seven predetermined frequency ranges are sequentially applied to the adjustable band pass filter 1342, the waveform of the signal S5 has seven different sections, each of which corresponds to one of the predetermined frequency ranges.
The frequency detection module 1344 then determines the wobble carrier frequency of the optical disk according to the signal S5. The frequency detection module 1344 includes an envelope detection module 1402 and a max amplitude selection module 1404. The envelope detection module 1402 detects the envelope of the signal S5 to obtain an envelope signal S6, which is shown in FIG. 15c. The envelope signal S6 of FIG. 15c has seven amplitudes h1˜h7 corresponding to the seven predetermined frequency ranges. Because the envelope signal S6 is the envelope of the filtered signal S5, the amplitude of the envelope signal S6 reflects the amount of the signal S3 surviving the filtration of the adjustable band pass filter 1342. The larger the amplitude, the more intense the signal S5 after filtration, the more the signal S3 passing the adjustable frequency range, and the closer the center frequencies of the major frequency band of signal S3 and the adjustable frequency range. Thus, the wobble carrier frequency is the center frequency of the adjustable frequency range according to which the filtered signal S6 section with the maximum amplitude is generated. Referring to FIG. 15b, the center frequency of the filtered signal S6 section with the maximum amplitude is fs4, and fs4 is therefore the wobble carrier frequency of the optical disk. The wobble carrier frequency fs4 is determined by the max amplitude selection module 1404, which monitors the envelope signal S6 to determine the maximum amplitude h4, and determines the center frequency fs4 of the adjustable frequency range corresponding to the maximum amplitude h4. Thus, fs4 is detected as the wobble carrier frequency.
FIG. 16 is a block diagram of an apparatus 1600 for identifying the disk format of an optical disk according to the invention. The apparatus 1600 is a sub-module of the frequency detection and disk format identification module 1304 of FIG. 3. The principle according to which the apparatus 1600 functions is similar to that of the apparatus 1400. Because each format of optical disk has a distinctive wobble carrier frequency, the optical disk format is identified if the wobble carrier frequency is determined. Thus, the apparatuses 1600 and 1400 share most modules thereof. The apparatus 1600 includes the anti-alias filter 1332, the offset canceller 1334, the binary conversion module 1336, the adjustable band pass filter 1342, and a disk format identification module 1346. The disk format identification module 1346 includes an envelope detection module 1602 and a max amplitude selection module 1604. Except the selection signal of the adjustable band pass filter 1342, the modules of the apparatus 1600 are similar to those of the apparatus 1400.
Because there is only a finite number of optical disk formats, such as DVD+R, DVD-R, DVD-RAM, DVD-RW, and DVD+RW, the potential wobble carrier frequencies corresponding to the potential disk types are sequentially assigned as the center frequency of the adjustable frequency range of the adjustable band pass filter 1342 of FIG. 16. The adjustable band pass filter 1342 then filters the data stream S4 generated by the binary conversion module 1336 according to the adjustable frequency range to generate a filtered signal S5. The disk format identification module 1346 then determines the maximum amplitude of the filtered signal S5, and determines the potential disk format corresponding to the potential wobble carrier frequency according to which the filtered signal with the maximum amplitude is generated. This is achieved by first detecting the envelope of the filtered signal with the envelope detection module 1602 to obtain an envelope signal S6, and then monitoring the envelope signal S6 with the max amplitude selection module 1604 to obtain the maximum amplitude. The max amplitude selection module 1604 then outputs the potential disk format corresponding to the maximum amplitude as the disk format of the optical disk. Thus, the optical disk format is identified.
FIG. 17 is a flowchart of a method 1700 for detecting the wobble carrier frequency of an optical disk according to the invention. A push-pull processor generates a first wobble signal of the optical disk in step 1702. The direct current offset of the first wobble signal is then canceled in step 1704 to obtain a second wobble signal S3. The second wobble signal S3 is then converted to a binary data stream S4 in step 1706. The binary data stream S4 is then filtered according to an adjustable frequency range in step 1708 to generate a filtered signal S5, wherein the center frequency of the adjustable frequency range is sequentially adjusted according to a frequency selection signal. A maximum amplitude of the filtered signal S5 is then determined in step 1710, and the center frequency of the adjustable frequency range according to which the filtered signal S5 with the maximum amplitude is generated is determined in step 1712. If no disk format is required to identify in step 1714, the center frequency corresponding to the maximum amplitude is then output as the wobble carrier frequency in step 1718. Otherwise, a disk format corresponding to the maximum amplitude of the filtered signal S5 is determined and the disk format is output in step 1716. Thus, both the wobble carrier frequency and the disk format of the optical disk are obtained.
The invention provides an apparatus for detecting the wobble carrier frequency and identifying the disk format of an optical disk. The noise existing in the wobble signal does not deteriorate the precision of the wobble carrier frequency. Thus, the performance of the wobble carrier frequency detection circuit provided by the invention is superior to the conventional circuit. In addition, because the adjusted band pass filter is a digital filter with simpler design and smaller chip area than the analog band pass filter in the conventional method, the manufacturing cost of the wobble carrier frequency detection circuit provided the invention is less than the conventional circuit.
FIG. 18 is an exemplary block diagram of a wobble detection circuit 1800 according to the invention. Because the signals SAD0 and SBC0 comprise high frequency noise induced by radio frequency signals and low frequency noise induced by servo signals, the low pass filters 1802 and 1812 and the high pass filters 1804 and 1814 respectively eliminate the high frequency noise and the low frequency noise from the signals SAD0 and SBC0, and signals SAD2 and SBC2 are obtained.
Two automatic gain controllers 1806 and 1816 then amplify the signals SAD2 and SBC2 to the same signal level to obtain signals SAD3 and SBC3. The automatic gain controllers 1806 and 1816 are implemented with digital automatic gain controllers provided by the invention to simplify circuit complexity. An adder module 1820 then subtracts the signal SBC3 from the signal SAD3 to obtain a wobble signal W0. The more balanced the signals SBC3 and SAD3 is, the less radio frequency noise remains in the wobble signal W0. After the wobble signal W0 passes a low pass filter 1822 to obtain a wobble signal W1, an address in pre-groove (ADIP) detector 1824 derives ADIP information from the wobble signal W1. Additionally, after the wobble signal W0 passes a band pass filter 1832 to obtain a wobble signal W2, a wobble phase locked loop 1834 locks the phase of the wobble signal W2 to generate a clock signal [ ]not shown.
FIG. 19 is a block diagram of a digital automatic gain controller 1900 according to the invention. The digital automatic gain controller 1900 includes an envelope detection module 1902, an analog to digital converter 1904, a digital control module 1906, a digital to analog converter 1908, and a variable gain amplifier 1910. The variable gain amplifier 1910 amplifies an input signal SI according to an analog gain signal M′ to obtain an amplified signal SO. The input signal SI can be the signal SAD2 or the signal SBC2 of FIG. 18, and the amplified signal SO can correspondingly be the signal SAD3 or the signal SBC3 of FIG. 18. The envelope detection module 1902 then detects an envelope magnitude E of the amplified signal SO. The analog to digital converter 1904 then converts the envelope magnitude signal E from analog to digital to obtain a digital envelope signal E′. Because the high frequency noise of envelope signal E does not as large as the amplified signal SO, and the analog to digital converter 1904 need not sample the envelope magnitude signal E with as high sampling frequency as the analog to digital converter 504 of FIG. 5.
The digital control module 1906 then determines a digital gain signal M for amplification of the input signal SI according to the digital envelope signal E′. After the digital to analog converter 1908 converts the digital gain signal M to analog gain signal M′, the variable gain amplifier 1910 can amplify the input signal SI according to the analog gain signal M′ to obtain the amplified signal SO. The low sampling rate of the analog to digital converter 1904 decreases the sampling rate of the digital envelope signal E′ and the digital gain signal M, further simplifying the circuit complexity and signal processing of the analog to digital converter 1904, the digital control module 1906, and the digital to analog converter 1908. Thus, compared to the digital automatic gain controller 500 of FIG. 5, the digital automatic gain amplifier 1900 requires less hardware cost.
FIG. 20 is a block diagram of a digital automatic gain controller 2000 with low sampling rate according to the invention. The envelope detection module 2002 includes a peak detection module 2012, a bottom detection module 2014, and an adder 2016. The peak detection module 2012 detects a peak magnitude P of the amplified signal SO. The bottom detection module 2014 detects a bottom magnitude B of the amplified signal SO. The adder 2016 then subtracts the bottom magnitude B from the peak magnitude P to obtain an envelope magnitude E. An analog to digital converter 2004 then converts the envelope magnitude E to a digital envelope signal E′. FIG. 21a shows an amplified signal SO, and FIG. 21b shows a digital envelope signal E′ derived from the amplified signal SO of FIG. 21a by the envelope detection module 2002 and the ADC 2004.
The digital envelope signal E′ is then delivered to a digital control module 2006. The digital control module 2006 includes an adder 2022, a gain controller 2024, and an integrator 2026. The adder 2022 subtracts the digital envelope signal E′ from a reference level R to obtain a difference signal D. The gain controller 2024 then reduces the magnitude of the difference signal D to a lower level to obtain a difference signal D′. The integrator 2026 then integrates the difference signal D′ to obtain the digital gain signal M. FIG. 21c shows a difference signal D corresponding to the digital envelope signal E′ of FIG. 21b when the reference level is 1. FIG. 21d shows a digital gain signal M derived from the difference signal D of FIG. 21c by the digital control module 2006. Finally, a digital to analog converter 2008 converts the digital gain signal M to an analog gain signal M′ for the amplification of an input signal SI. Thus, a variable gain amplifier 1910 can then amplify the input signal SI according to the analog gain signal M′ to obtain the amplified signal SO.
FIG. 22 is another block diagram of a digital automatic gain controller 2200 with low sampling rate according to the invention. The digital automatic gain controller 2200 differs from digital automatic gain controller 2000 of FIG. 20 only in the envelope detection module 2202. The envelope detection module 2202 includes a rectifier 2212 and a low pass filter 2214. The rectifier 2212 first generates an absolute value signal I of an amplified signal SO The low pass filter 2214 then eliminates high frequency noise from the absolute value signal I to obtain the envelope magnitude E. FIG. 23a shows an amplified signal SO, and FIG. 23b shows an envelope magnitude E derived from the amplified signal SO of FIG. 23a by the envelope detection module 2202. An analog to digital converter 2204 then converts the envelope magnitude to a digital envelope signal shown in FIG. 23c. A digital control module 2206 then derives a digital gain signal M from the digital envelope signal E′. FIG. 23d shows a difference signal D corresponding to the digital envelope signal E′ of FIG. 23c, and FIG. 23e shows a digital gain signal M derived from the difference signal D of FIG. 23d by the digital control module 2206. Finally, a digital to analog converter 2208 converts the digital gain signal M to an analog gain signal M′ for the amplification of an input signal SI. Thus, a variable gain amplifier 1910 can then amplify the input signal SI according to the analog gain signal M′ to obtain the amplified signal SO.
Because input signals of the analog to digital converters 2004 and 2204 are the envelope signals E, the sampling rate of the analog to digital converters 2004 and 2204 is lower than the analog to digital converter 504 of FIG. 5. To obtain precise gain signal, the signal resolution of the analog to digital converters 2004 and 2204 remains high. This can be observed with the digital envelope signals shown in the FIG. 21b and FIG. 23c with a high signal resolution. The signal resolution, however, can be reduced in the increase of sampling rate. FIG. 24 is a detailed block diagram of a digital automatic gain controller 2400 with low signal resolution and high sampling rate according to the invention.
The digital automatic gain controller 2400 includes an envelope detection module 2402, an adder 2403, a 1-bit analog to digital converter 2404, a digital control module 2406, a digital to analog converter 2408. The envelope detection module 2402 includes a rectifier 2412 which calculates an absolute value of an amplified signal SO and outputs the absolute value as an envelope magnitude E. FIG. 25a shows an amplified signal SO, and FIG. 25b shows an envelope magnitude E derived from the amplified signal SO of FIG. 25a by the rectifier module 2412. The adder 2403 then subtracts the envelope magnitude E from a reference level R to obtain a difference signal D. Because the envelope signal E is not processed by a low pass filter as in FIG. 22, the envelope signal E and the difference signal D oscillate with the frequency of the amplified signal SO. Thus, the 1-bit ADC 2404 convert the analog difference signal D to a 1-bit data stream D′ with a sampling frequency more than double the frequency of the amplified signal SO.
FIG. 25
c shows a 1-bit difference data stream D′ corresponding to the envelope magnitude E of FIG. 25b. Although the sampling rate of the ADC 2404 is high, because the 1-bit data stream D′ has only two values, the signal resolution of the 1-bit data stream D′ converted by ADC 2404 is lower than the signal resolution of the digital envelope signals E′ of ADC 2404 and 2204, as shown in FIGS. 23c and 21b. The difference signal D′ in the form of 1-bit data stream is then delivered to the digital control module 2406, which includes a gain controller 2424, and an integrator 2426. The gain controller 2424 first reduces the magnitude of the difference signal D′ to a lower level to obtain a difference signal D″. The integrator 2426 then integrates the difference signal D″ to obtain the digital gain signal M. FIG. 25d shows a digital gain signal M derived from the difference signal D′ of FIG. 25c by the digital control module 2406. Finally, a digital to analog converter 2408 converts the digital gain signal M to an analog gain signal M′ for amplification of an input signal SI. Thus, a variable gain amplifier 1910 can then amplify the input signal SI according to the analog gain signal M′ to obtain the amplified signal SO.
The invention provides a digital automatic gain controller amplifying a signal. Conventional digital automatic gain controllers process signals at high sample rates and high signal resolution to provide good quality of amplified signals. The digital automatic gain controller provided by the invention, however, can process signals at low sample rates or low signal resolution while obtaining amplified signals of the same quality. The lower sample rates and the lower signal resolution simplify signal processing process and circuit design, improving performance of the digital automatic gain controller and reducing hardware costs.
FIG. 26 is a block diagram of an apparatus 2600 for demodulating ADIP symbols according to the invention. The apparatus 2600 includes a wobble extraction module 2602, a reference wobble generator 2604, a waveform difference measurement module 2606, and a pattern matching module 2608. The wobble extraction module 2602 first derives a wobble signal from a source signal reflected from the track surface of an optical disk. In one embodiment, the wobble extraction module 2602 is a push-pull processor which subtracts a reflection intensity reflected by one side of a track from another reflection intensity reflected by the other side of the track to obtain the wobble signal. After the wobble signal is generated, the reference wobble generator 2604 generates a reference wobble, with the same frequency and phase as a fundamental frequency and phase of the positive wobble cycle of the wobble signal. Referring to FIG. 27, the first row and second row of FIG. 27 respectively show the waveforms of the reference wobble and the wobble signal. In one embodiment, the reference wobble generator 2604 is a phase lock loop repeating the positive wobble cycle of the wobble signal to generate the reference wobble.
The waveform difference measurement module 2606 then measures a difference between the wobble signal and the reference wobble to obtain a series of difference measurement values. In one embodiment, the difference is a phase difference. Since each difference measurement value is determined according to a corresponding wobble cycle of the wobble signal, each of the difference measurement values therefore respectively corresponds to one ADIP bit. Referring to FIG. 27, the third and fourth rows of FIG. 27 respectively show the phase difference and the obtained difference measurement values. Because the reference wobble has the same phase as that of an positive wobble cycle of the wobble signal, there is almost no difference between a wobble cycle of the wobble signal and the reference wobble if the wobble cycle is a positive wobble cycle, and the obtained difference measurement value is small. Otherwise, if the wobble cycle is a negative wobble cycle, the obtained difference measurement value is large.
FIG. 28 is a block diagram of a waveform difference measurement module 2800 according to the invention. The waveform difference measurement module 2800 includes a phase comparator 2802 and a counter 2804. The phase comparator 2802 first compares the phases of the wobble signal and the reference wobble to obtain a phase difference signal. In one embodiment, the phase comparator 2802 is an XOR gate which performs an XOR operation on the wobble signal and the reference wobble to obtain the phase difference signal. Because the XOR gate only generates a high level voltage when both the wobble signal and the reference wobble are at the high level or low level, the generated phase difference signal can appropriately reflect the difference between the wobble signal and the reference wobble. The counter 2804 then counts a high level width of the phase difference signal during each wobble cycle of the reference wobble to generate the difference measurement values corresponding to the ADIP bits. The counter counts the high level width according to a clock signal having a frequency higher than that of the reference wobble. For example, the difference measurement values shown in the fourth row of FIG. 27 can be obtained according to a clock signal with the frequency which is 16 times the wobble cycle frequency of the reference wobble. Thus, the obtained difference measurement values lie between 0 and 16 and reflect the difference levels during each wobble cycle.
After the difference measurement values are generated, the pattern matching module 2608 then compares probabilities of the permutation of the ADIP bits agreeing with each of the permutation patterns according to the difference measurement values to determine the ADIP symbols carried by the wobble signal. FIG. 29 is a block diagram of a pattern matching module 2900 according to the invention. The pattern matching module 2900 includes a collector 2902, a correlator array 2904, and a maximum likelihood comparison module 2906. Because each ADIP symbol is composed of eight ADIP bits and the permutation pattern of the eight ADIP bits determines which a ADIP symbol is, the collector 2902 collects eight successive difference measurement values to be compared with the probable permutation patterns of the ADIP bits. The correlator array 2904 includes multiple correlators, each of which correlates the difference measurement values with signs derived from a probable permutation pattern of the ADIP bits to obtain correlation values and then sums the correlation values corresponding to the permutation pattern to obtain the probabilities that the ADIP bits are permutated according to the corresponding permutation pattern.
For example, the eight difference measurement values shown in the fourth row of FIG. 27 are 14, 2, 1, 3, 2, 0, 15, and 11. Because the permutation pattern corresponding to ADIP data 0 symbol is “10000011”, the derived correlation values are therefore 14, −2, −1, −3, −2, 0, 15, and 11, and the summation thereof is therefore 32, which indicates the probability that the corresponding ADIP bits represents the ADIP data 0 symbol. The permutation pattern corresponding to ADIP data 1 symbol is “10001100”, the derived correlation values are therefore 14, −2, −1, −3, 2, 0, −15, and −11, and the probability that the corresponding ADIP bits represents the ADIP data 1 symbol is therefore −16. Accordingly, the permutation pattern corresponding to ADIP synch symbol is “11110000”, and the probability that the corresponding ADIP bits represent the ADIP synch symbol is therefore −8.
The maximum likelihood comparison module 2906 then compares the probabilities corresponding to the permutation patterns to determine the ADIP symbol. The maximum likelihood comparison module 2906 includes three comparators 2922, 2924, and 2926 and three AND gates 2932, 2934, and 2936. The comparators 2922, 2924 and 2926 respectively compare two of the three probabilities generated by the correlator array 2904 to determine comparison results indicating the larger of the two probabilities. Each of the AND gates 2932, 2934, and 2936 then performs an AND operation on two of the comparison results to determine which of the permutation patterns has the largest probability, and the permutation pattern with the largest probability determines the ADIP symbol. For example, if the probabilities corresponding to the ADIP data 0 symbol, the ADIP data 1 symbol, and the ADIP synch symbol in FIG. 6 are respectively 32, −16, and −8, the largest probability of 32 indicates that the ADIP symbol is an ADIP data 0 symbol.
FIG. 30 is a flowchart of a method 3000 for demodulating ADIP symbols according to the invention. First, a wobble signal is generated at step 3002. A reference wobble with the same frequency and phase as a fundamental frequency and phase of a positive wobble cycle of the wobble signal is then generated at step 3004. A phase difference between the wobble signal and the reference wobble is then measured at step 3006 to obtain a series of difference measurement values respectively corresponding to the ADIP bits. The difference measurement values are then correlated with the signs derived from the probable permutation patterns of the ADIP bits to obtain correlation values at step 3008, and the correlation values corresponding to each permutation patterns are then summed to determine the probabilities that the ADIP symbol conforms to each of the permutation pattern at step 3010. Finally, an ADIP symbol is determined according to the permutation pattern with the largest probability at step 3012.
The method 3000 not only demodulates the ADIP symbols of optical disks with the format of DVD+R or DVD+RW, but can further be applied to demodulate ADIP symbols of HD-DVD optical disks. According to the HD-DVD specification, the ADIP symbol is made up of a single ADIP bit which may be a Normal Phase Wobble (NPW) or an Invert Phase Wobble (IPW). Thus, the pattern matching module 2608 of the apparatus 2600 is substituted by a slicer to generate the ADIP symbol, because a single ADIP bit has only two selective permutations of NPW or IPW, which can be determined by only a slicer or a decision maker [no shown]. FIG. 31 shows the apparatus 3100 for demodulate ADIP symbols of HD-DVD disks according to the invention. Except for the slicer 3108, all other three elements of the apparatus 3100 are substantially the same as the corresponding ones of the apparatus 2600.
Based on the principle of the apparatus 2600 for demodulating ADIP symbols, an apparatus 3200 for demodulating pre-pit symbols is provided. FIG. 32 is a block diagram of the apparatus 3200 for demodulating pre-pit symbols according to the invention. The apparatus 3200 includes a pre-pit bit collection module (not shown in FIG. 32), a hamming distance generator array 3202, and a pattern decision module 3204. A wobble signal carrying pre-pit bits is first extracted from an optical disk. Because the pre-pit bits only appear at either an odd frame or an even frame of the wobble signal, the pre-pit bit collection module then collects the pre-pit bits appearing at both an odd frame and an even frame to obtain a pre-bit bit set. Referring to FIG. 9, the three pre-pit bits have “111” permutation pattern for pre-pit synch symbol in even frame, “110” permutation pattern for pre-pit synch symbol in odd frame, “101” permutation pattern for pre-pit data 1 symbol, or “100” permutation pattern for pre-pit data 0 symbol. Thus, if the pre-pit bit collection module collects pre-pit bits in the order of an even frame followed by an odd frame, there may be six type of permutation patterns of the pre-pit bits collected by the pre-pit bit collection module: “111000” for pre-pit synch symbol in even frame, “000110” for pre-pit synch symbol in odd frame, “101000” for pre-pit data 1 symbol in even frame, “000101” for pre-pit data 1 symbol in odd frame, “100000” for pre-pit data 0 symbol in even frame, and “000100” for pre-pit data 0 symbol in odd frame.
The hamming distance generator array 3202 then measures a plurality of hamming distances between the pre-pit bits of the pre-bit set and each of the permutation patterns, “111000”, “000110”, “101000”, “000101”, “100000”, and “000100”. The hamming distance generator array 3202 includes a plurality of hamming distance generators 3212, 3214, 3222, 3224, 3232, and 3234, each of which measures a hamming distance between the pre-pit bits of the pre-bit set and one of the permutation patterns. Because a hamming distance indicates the number of bits located at the same location of two strings but having different values, the hamming distance appropriately reflects the probability that the pre-pit bits represent a pre-pit symbol, just like the sum of the correlation values generated by the correlator array 2912 in FIG. 29. The pattern decision module 3204 then finds the permutation pattern having a minimum of the hamming distances to determine the pre-pit symbol represented by the pre-pit bits. Thus, the pre-pit symbol is determined.
The invention provides methods for demodulating ADIP symbols and pre-pit symbols carried by a wobble signal. The ADIP symbols record addressing information for optical disks with the format of DVD+R or DVD+RW, and the pre-pit symbols record addressing information for optical disks with the format of DVD-R or DVD-RW. Because the probabilities that the ADIP bits or the pre-pit bits agree with the specific permutations of probable ADIP symbols or pre-pit symbols are appropriately measured with sums of correlation values or hamming distances to determine the output ADIP symbols or pre-pit symbols, the noise tolerance of the methods provided by the invention is much higher than that of conventional methods, and the performance and precision of the demodulation of ADIP symbols and pre-pit symbols are greatly improved.
Please refer to FIGS. 33a and 33b. FIGS. 33a and 33b respectively show the exemplary synthesized signals SAD and SBC retrieved from blank sectors and non-blank sectors. As disclosed above, a pick-up head detects four reflection signals SA, SB, SC, and SD reflected from an optical disk, wherein signals SA, SD and signals SB, SC are respectively representing light intensity reflected from the opposite sides of a track. The reflection signals SA and SD are then added to obtain a signal SAD and the reflection signals SB and SC are then added to obtain a signal SBC. The left segment of FIGS. 33a and 33b represents intensity of reflected light from corresponding blank sectors, and the right segment of FIGS. 33a and 33b represents intensity of reflected light from corresponding non-blank sectors.
Please refer to FIG. 33c, FIG. 33d and FIG. 34. FIG. 33c shows a wobble peak signal drives by a peak detection unit of FIG. 34. FIG. 33d shows a blank detection signal. FIG. 34 is an exemplary block diagram of an apparatus 3400 for detecting the blank sector on an optical disk using the wobble signals. Apparatus 3400 includes a push-pull processor 3402, similar to push-pull processor 1302 in FIG. 13, for generating the wobble signal B1, a low pass filter 3404 for filtering high frequency noises to generate a filtered wobble signal B2, and a blank detection module 3406 receiving the filtered wobble signal B2 for generating a blank detection signal to determining the corresponding blank sectors of the optical disk. The blank detection module 3406 further includes a peak detection unit 3408 for detecting envelop of the filtered wobble signal B2 to generate wobble peak signal B3, as shown in FIG. 33c. In addition, a comparator 3410 compares the filtered wobble signal B2 with a threshold value to generate the blank signal B4, as Shown in FIG. 33d. The comparator 3410 can be a slicer or a decision maker, thus the blank detection apparatus determines the corresponding blank sectors of the optical disk in accordance with the wobble signals.
Because the wobble signal B1 is generated by subtracting the signal SBC from signal SAD, the problem of diverse amplitude levels of RF signal between various disks is solved. Therefore, the unick threshold value of the comparator can utilized for various disks.
FIG. 35 is a flow chart of the blank detection method. In step 3502, a push-pull processor generates a wobble signal of the optical disk. The high frequency noises of the wobble signal are filtered to generate a filtered wobble signal in step 3504. Then, in step 3506, a peak detection unit detect envelop of the filtered wobble signal to generate wobble peak signal. Finally, in step 3508, a comparator compares the wobble peak signal with a threshold value to generate the blank signal. The blank signal determines the corresponding blank sectors of the optical disk.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Patent Application
20070280069
