Claims
- 1. An integrated circuit, comprising:
a die; an active area disposed on said die, said active area including source dopants and contacts, an active area metal layer overlying said active area; a sense area disposed on said die, a sense area metal layer overlying said sense area; a plurality of polysilicon gate stripes, polysilicon openings, and body stripes disposed on said die, said plurality of polysilicon gate stripes, polysilicon openings, and body stripes extending in a continuous and uninterrupted manner from said active area into said sense area; a first region surrounding a periphery of said sense area, said first region having excluded therefrom source dopants and contacts; an etched region disposed over said first region, said etched region separating and electrically isolating said sense area metal layer from said active area metal layer.
- 2. The integrated circuit of claim 1, wherein said integrated circuit is a transistor.
- 3. The integrated circuit of claim 2, wherein said transistor is one of an integrated gate bipolar transistor and a metal oxide field effect transistor.
- 4. The integrated circuit of claim 2, wherein said transistor is a trench stripe device.
- 5. The integrated circuit of claim 1, further comprising a control circuit integral and monolithic with said die and configured for being electrically connected to said sense area.
- 6. The integrated circuit of claim 1, wherein said sense area comprises a source exclude region from which source dopants have been excluded.
- 7. The integrated circuit of claim 6, wherein said sense area further comprises a source region, said source region doped with source dopants.
- 8. The integrated circuit of claim 7, wherein said source region surrounds said source exclude region, said first region surrounding said source region.
- 9. On an integrated circuit die, a method of isolating a current sense area from a main device active area while maintaining a continuous stripe cell, the sense area having an overlying sense metal layer, the main device active area having an overlying active metal layer, said method comprising:
fabricating on the die a plurality of polysilicon gate stripes, polysilicon openings, and body stripes that extend in a continuous and uninterrupted manner from the active area into the sense area; excluding source dopants and contact from a first region that surrounds the periphery of the sense area; and breaking the active area metal layer over the first region to thereby electrically isolate the sense area from the active area.
- 10. The method of claim 9, wherein said first region extends at least partially into each of said sense area and said main device area.
- 11. The method of claim 9, comprising the further step of excluding source dopants from a source exclude region of the sense area.
- 12. The method of claim 11 comprising the further step of doping a source region of the sense area with source dopants.
- 13. The method of claim 12, wherein said source region surrounds said source exclude region.
- 14. The method of claim 9, wherein said breaking step comprises etching the active area metal layer over the first region.
- 15. The method of claim 9, comprising the further step of electrically connecting said sense area to a control circuit integral and monolithic with the die.
- 16. The method of claim 9, wherein the integrated circuit is one of an integrated gate bipolar transistor and a metal oxide field effect transistor.
- 17. The method of claim 16, wherein the transistor is a trench stripe device.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional Patent Application Serial No. 60/350,861, filed Jan. 22, 2002.
Provisional Applications (1)
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Number |
Date |
Country |
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60350861 |
Jan 2002 |
US |