Patent Application
20160335385
The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC design and material have produced generations of ICs where each generation has scaled down to smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased.
This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC processing and manufacturing. For these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, improvements to the IC design layout are needed.
Aspects of the present disclosure are best understood from the following detailed description when read in association with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features in the drawings are not drawn to scale. In fact, the dimensions of illustrated features may be arbitrarily increased or decreased for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The design house (or design team) 120 generates an IC design layout 122. The IC design layout 122 includes various geometrical patterns (features) designed for an IC product, based on a specification of the IC product to be manufactured. The geometrical patterns correspond to patterns of materials that make up the various components of the IC device 160 to be fabricated. For example, a portion of the IC design layout 122 includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design house 120 implements a proper design procedure to form the IC design layout 122. The design procedure may include logic design, physical design, and/or place and route. The IC design layout 122 is presented in one or more data files having information about the geometrical patterns. For example, the IC design layout 122 can be expressed in a GDSII file format (or DFII file format).
The mask house 130 uses the IC design layout 122 to manufacture one or more masks to be used for fabricating the various layers of the IC product according to the IC design layout 122. The mask house 130 performs mask data preparation 132 and mask fabrication 144. Mask data preparation 132 involves the IC design layout 122 being translated into a form that can be physically written by a mask writer. Mask fabrication 144 involves using the design layout prepared by the mask data preparation 132 being modified to comply with a particular mask writer and/or mask manufacturer and then subsequently fabricating the mask. In the present embodiment, the mask data preparation 132 and mask fabrication 144 are illustrated as separate elements, however, the mask data preparation 132 and mask fabrication 144 can be considered one element that is collectively referred to as a mask data preparation element.
The mask data preparation 132 may include an optical proximity correction process (OPC) 138 and a lithography process check process (LPC) 140. The OPC 138 is a lithography enhancement technique used to compensate for image errors, such as those that can arise from diffraction, interference, and/or other process effects. OPC 138 may add features, such as scattering bars (SBs), serif, and/or hammerheads to the IC design layout 122 according to optical models and/or rules such that, after a lithography process, a final pattern on a wafer is improved with enhanced resolution and precision. The mask data preparation 132 according to an illustrated embodiment is described in greater detail below. The mask data preparation 132 also includes further resolution enhancement techniques, such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and/or combinations thereof.
The LPC 140 simulates processing that will be implemented by the IC manufacturer 150 to fabricate the IC device 160. The LPC 140 simulates this processing based on the IC design layout 122 to create a simulated manufactured device, such as the IC device 160. The simulated manufactured device includes simulated contours of a portion and/or the entire IC design layout. In the present embodiment, the LPC 140 simulates processing of the modified IC design layout, which has been subjected to the OPC 138. The LPC 140 uses one or more LPC models (or rules) 142. The LPC models 142 may be based on actual processing parameters of the IC manufacturer 150. The processing parameters can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC 140 takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error sensitivity in the form of a mask error enhancement factor (“MEEF”), other suitable factors, and/or combinations thereof.
After a simulated (or virtual) device has been created by the LPC 140, if the simulated device is not close enough in shape to satisfy design rules, certain steps in the mask data preparation 132, such as OPC 138, may be repeated to refine the IC design layout 122 further. It should be understood that the above description of the mask data preparation 132 has been simplified for the purposes of clarity, and data preparation may include additional features such as a logic operation (LOP) to modify the IC design layout according to manufacturing rules, a retarget process (RET) to modify the IC design layout to compensate for limitations in lithographic processes used by IC manufacturer 150, and a mask rule check (MRC) to modify the IC design layout to compensate for limitations during mask fabrication 144. Additionally, the processes applied to the IC design layout 122 during data preparation 132 may be executed in a variety of different orders.
During mask fabrication 144, a mask and/or a group of masks are fabricated based on the modified IC design layout. For example, an electron-beam (e-beam) and/or a mechanism of multiple e-beams is used as an exposure source to form a pattern on a mask (photomask or reticle) based on the modified IC design layout. The IC manufacturer 150 uses the mask (or masks) fabricated by the mask house 130 to transfer the IC design to a semiconductor substrate 152, such as a wafer, to form the IC device 160.
Referring to
In the present embodiment, the main features 310 include a plurality of square-shape main features 310. In some embodiments, each of the main features 310 has a same width. In some embodiments, main features 310 have different widths. In some embodiments, a distance D between each of two adjacent main features 310 is same. In some embodiments, the distance D varies among the main feature 310.
Usually, an optical proximity correction process (OPC) is applied to the IC design layout 300 to compensate for distortions caused by diffraction of radiation that occurs during the use of the lithography tools. The OPC process may include applying features that will alter the photomask, such as adding sub-resolution features to the photomask that interact with the original patterns in the physical design, adding features to the original patterns such as “serifs,” adding jogs to features in the original pattern, modifying main feature pattern shapes or edges, and/or other enhancements. As process nodes shrink, OPC processes and the resultant patterns become more complex. Although existing OPC processes have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, one type of advanced OPC process is inverse lithography technology (ILT). ILT includes simulating the optical lithography process in the reverse direction, using the desired pattern on the substrate as an input to the simulations. The ILT process may produce complex, non-linear patterns that can be difficult, time consuming, and/or costly to form on a photomask or reticle. For another example, another type of advanced OPC process is adding scattering bars (SBs) to the IC design layout, but doing so induces focus shifting. The present disclosure provides an OPC process that includes inserting SBs with an arrangement that reduces focus shifting in comparison to previous attempts involving the insertion of SBs.
Referring to
In the present embodiment, a respective ESBoC arrangement is assigned to each of the main features 310. In this example, the total number of SBs of each ESBoC arrangement is equal to N×8, where N is an integer.
In other examples, a given SB 410 may be part of (i.e. assigned to) more than one ESBoC arrangement. That is, as shown and discussed below in
Each individual SB 410 can have a square-shape, rectangular shape, and/or any other suitable shape. As shown in
Referring to
As shown in
Referring to
As shown in
When the radius R is chosen to be equal to a half of a distance between the main features 310a and 310e, two adjacent SB circles C of main features 310a and 310e, 310b and 310e, 310c and 310e, 310d and 310e, overlap at locations of O, P, S, T, respectively, shown in
Referring to
A first subgroup of the SB 410, SB 410A, is positioned in a first circle C1 and a second subgroup of the SB 410, SB 410B, is positioned in a second circle C2, such that the first SBs 410A are positioned similarly in the first circle C1 with respect to the second SBs 410B in the second SB circle C2. The first circle C1 has a first radius R1 and the second SB circle has a second radius R2. The second SB 410B has a similar same shape (i.e. square), but different size as compared to the first SB 410A. The first SB410A has a third area A3 and the second SB 410B has a fourth area A4. Here, the fourth area A4 is greater than the third area A3, For example, a ratio of the fourth area A4 to the third area A3 is in a range of greater than 1 to less than 1.5. A range of the third area and the fourth area is in such way that: 0.1(w1)2<A3<A4<0.4(w1)2. In other embodiments, the fourth area A4 is same as the third area A3.
Here, the second radius R2 is chosen to be the same as the first radius R1. In the present embodiment, when the first and second circles, C1 and C2, overlap at a single location U (shown as
Additional steps can be provided before, during, and after the method 200, and some of the steps described can be replaced, eliminated, or moved around for additional embodiments of the method 200.
For example, after forming the modified IC design layout 500, it is provided to a mask writer. In one embodiment, the modified IC design layout 500 is provided in a mask writer format, such as a machine readable format. In another embodiment, one or more of aspects of the design data is provided in a MEBES database format. The data provided to and/or used by the mask writer may be stored on a non-transitory storage medium. The mask writer may be an e-beam mask writer. In one embodiment, the e-beam mask writer is a multi-beam e-beam writer. Other exemplary e-beam writers include variable shaped beam writers, Gaussian beam, character projection, and/or other suitable e-beam writer tools. In other embodiments, the mask writer may be a laser writer.
For another example, after mask writer receives the modification design layout 500, it is used in a mask fabrication to form a geometric pattern corresponding to the modification design layout 500 on a mask. The mask writer, such as an e-beam writer, projects one or more beams of electrons through a stencil onto the mask (blank having a photosensitive layer) to form a mask image reflecting the patterns on the modification design layout 500 layout. It is noted that some features of the modification design layout 500, such as the SBs 410, may be sub-resolution. Thus, though they are formed on the photomask, they are not formed on the target substrate during the imaging.
The mask fabricated may include a substrate upon which patterns are etched and/or materials disposed thereon are patterned to reflect the modification design layout 500. The mask may be a binary mask, a phase shift mask (PSM), an extreme ultraviolet lithograph (EUVL) mask, and/or other suitable mask. In an embodiment, the mask includes transparent substrate (e.g., quartz) and an opaque material (e.g., chromium). Exemplary PSM may include attenuated PSM, alternating PMS, and/or other phase shift mask technologies. Exemplary EUL masks may include a substrate (e.g., quartz, a low-thermal expansion material (LTEM)) having various multilayers and absorption layers formed thereon.
Based on the above, the present disclosure offers a method for modifying IC design layout by inserting scattering bars. The method employs an ESBoC arrangement in inserting scattering bars. The method demonstrates improving DOF, SB printing out window and reducing focus shifting. The method provides a robust OPC process.
Thus, the present disclosure provides one embodiment of an integrated circuit (IC) method. The IC method includes receiving an IC design layout including a first main feature and inserting a first plurality of scattering bars in the IC design layout to form a first circular pattern of scattering bars around the first main feature. The first main feature is positioned at a center portion of the first circular pattern of scattering bars.
The present disclosure provides another embodiment of an IC method. The method includes receiving an IC design layout including a plurality of main features and inserting a plurality of scattering bar (SB)s in the IC design layout. Each of the main feature is surrounded by a subgroup of the SBs and each subgroup has 8N of the SB (here N is an integer). Each of the SB is positioned uniformly along a circle with the respective main feature as its center. The SBs in different subgroups are positioned in a similar position in the respective circles. The scattering bars have a same central angle between two adjacent SBs, which is equal to bout (360)/(8N), where N is an integer.
The present disclosure also provides another embodiment of an IC method. The method includes receiving an IC design layout including a first main feature and a second main feature. The first main feature and a second main feature have a same shape. The method also includes inserting a first subgroup of scattering bar (SB)s in the IC design layout. The first subgroup of the SBs is positioned uniformly along a first circle with the first main feature in its center. The method also includes inserting a second subgroup of the SBs in the IC design layout. The second subgroup of the SBs is positioned uniformly along a second circle with the first main feature in its center. Each of subgroup has 8N of the SB (here N is an integer). The SBs in the first subgroup are positioned in the first circle in a similar position as the SBs in the second subgroup in the second circle.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the detailed description that follows. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments disclosed herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
