Claims
- 1. A method of making a nanoscale electronic device wherein said device comprises:
a first material selected from the group consisting of conductors and semiconductors; optionally, a second material that is an insulator; a third material selected from the group consisting of conductors and semiconductors; and at least one molecular electronic component
wherein a gap between about 0.1 nm and about 100 nm exists between said first and third materials and said gap comprises at least one said molecular electronic component and, optionally, a portion of said second material, said method comprising:
(a) depositing a quantity of said first material in a given shape and orientation onto a substrate; (b) depositing a quantity of said second material onto said first material in a manner sufficient to obtain a uniform layer of desired thickness of said second material on said first material; (c) depositing a quantity of said third material onto said second material in a given shape and orientation such that when viewed from at least one direction said first, second and third materials share a common area of intersection; (d) removing at least a portion of the second material in such a manner as to create a gap between said first and third materials; and (e) adding at least one molecular electronic component to said gap.
- 2. The method according to claim 1 wherein said first material is a conductor comprising at least one selected from the group consisting of titanium, titanium nitride, zirconium, hafnium, vanadium, niobium, tantalum, tantalum nitride, chromium, tungsten, molybdenum, cobalt, rhodium, iridium, nickel, palladium, platinum, copper, silver, gold, aluminum and any combination thereof.
- 3. The method according to claim 1 wherein said first material is a conductor comprising at least one selected from the group consisting of titanium, palladium, platinum, copper, gold, aluminum and any combination thereof.
- 4. The method according to claim 1 wherein said first material is a semiconductor comprising at least one selected from the group consisting of silicon (Si), doped silicon, doped polysilicon, gallium and its compounds, compounds of arsenic, compounds of nitrogen, indium and its compounds, germanium and its compounds, gallium arsenide (GaAs), gallium nitride (GaN), titanium nitride (TiN), silicon carbide (SiC), aluminum phosphide (AlP), aluminum arsenide (AlAs), aluminum antimonide (AlSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), zinc sulfide (ZnS), zinc selenide (ZnSe), zinc telluride (ZnTe), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), lead sulfide (PbS), lead selenide (PbSe), lead telluride (PbTe) and any combination thereof.
- 5. The method according to claim 1 wherein said first material is a semiconductor comprising silicon doped with arsenic.
- 6. The method according to claim 1 wherein said first material further comprises at least one dopant selected from the group consisting of arsenic, phosphorus, antimony and boron.
- 7. The method according to claim 1 wherein said first material is deposited in the approximate shape of a wire.
- 8. The method according to claim 7 wherein said wire has a thickness between about 5 nm and about 1000 nm.
- 9. The method according to claim 7 wherein said wire has a thickness between about 100 nm and about 500 nm.
- 10. The method according to claim 1 wherein the insulating substrate is in the shape of a flat plane and said first material is in the shape of a wire wherein the primary axis of the wire is parallel with the plane of the substrate.
- 11. The method according to claim 1 wherein depositing a quantity of said first material onto said insulating substrate comprises:
depositing a layer of said first material onto said substrate; depositing a layer of a photoresist onto said first material; exposing said photoresist and first material to radiation of suitable wavelength via a patterned mask to imprint the shape desired for the first material; removing exposed photoresist and etching unprotected first material to leave photoresist and first material in desired pattern; and removing unexposed photoresist to leave desired pattern of first material.
- 12. The method according to claim 1 wherein the insulating substrate comprises at least one selected from the group consisting of silicon and gallium arsenide.
- 13. The method according to claim 1 wherein the insulating substrate is an organic polymer.
- 14. The method according to claim 1 wherein the insulating substrate is a reversed-biased p/n junction silicon wafer.
- 15. The method according to claim 1 wherein the insulating substrate is a silicon wafer.
- 16. The method according to claim 1 wherein said second material comprises an oxide of at least one selected from the group consisting of yttrium, lanthanum, titanium, zirconium, hafnium, tantalum, molybdenum, iridium, nickel, palladium, platinum, copper, gold, aluminum, gallium, indium, silicon, and germanium and any combination thereof.
- 17. The method according to claim 1 wherein said second material comprises a nitride of at least one selected from the group consisting of yttrium, lanthanum, titanium, zirconium, hafnium, tantalum, molybdenum, iridium, nickel, palladium, platinum, copper, gold, aluminum, gallium, indium, silicon and germanium and any combination thereof.
- 18. The method according to claim 1 wherein said second material comprises at least one material selected from the group consisting of yttrium oxide, lanthanum oxide, titanium(IV) oxide, zirconium(IV) oxide, hafnium(IV) oxide, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide and any combination thereof.
- 19. The method according to claim 1 wherein the thickness of the uniform layer is between about 0.1 nm and about 100 nm.
- 20. The process according to claim 1 wherein the thickness of the uniform layer corresponds to the dimension of the molecular monolayer formed from the molecular electronic component.
- 21. The method according to claim 20 wherein the distance of the gap between said first and third materials is between about 1 nm and about 50 nm.
- 22. The method according to claim 20 wherein the distance of the gap between said first and third materials is between about 1 nm and about 10 nm.
- 23. The method according to claim 1 wherein the roughness of the uniform layer exhibits a maximum peak height that projects no more than about 3 Å from the surface of the deposited second material.
- 24. The method according to claim 1 wherein the second material is deposited onto the first material using a technique of controlled oxide growth.
- 25. The method according to claim 24 wherein the technique of controlled oxide growth is atomic layer deposition (ALD).
- 26. The method according to claim 1 wherein said third material is a conductor comprising at least one selected from the group consisting of titanium, titanium nitride, zirconium, hafnium, vanadium, niobium, tantalum, tantalum nitride, chromium, tungsten, molybdenum, cobalt, rhodium, iridium, nickel, palladium, platinum, copper, silver, gold, aluminum and any combination thereof.
- 27. The method according to claim 1 wherein said third material is a conductor comprising at least one selected from the group consisting of titanium, palladium, platinum, copper, gold, aluminum and any combination thereof.
- 28. The method according to claim 1 wherein said third material is a semiconductor comprising at least one selected from the group consisting of silicon (Si), doped silicon, doped polysilicon, gallium, and its compound, compound of arsenic, compounds of nitrogen, indium and its compound, germanium and its compounds, gallium arsenide (GaAs), gallium nitride (GaN), titanium nitride (TiN), silicon carbide (SiC), aluminum phosphide (AlP), aluminum arsenide (AlAs), aluminum antimonide (AlSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), zinc sulfide (ZnS), zinc selenide (ZnSe), zinc telluride (ZnTe), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), lead sulfide (PbS), lead selenide (PbSe), lead telluride (PbTe), and any combination thereof.
- 29. The method according to claim 1 wherein said third material is a semiconductor comprising polysilicon doped with arsenic.
- 30. The method according to claim 1 wherein the gap between said first and third materials exists substantially near the edge of said area of intersection.
- 31. The method according to claim 1 wherein substantially all of the second material in said common area of intersection is removed to create a gap between said first and third materials.
- 32. The method according to claim 1 wherein the molecular electronic component exhibits behavior corresponding to at least one selected from the group consisting of resistor, diode, conductor, capacitor, resonant tunneling diode and resonant tunneling resistor.
- 33. The method according to claim 1 wherein the molecular electronic component comprises at least one selected from the group consisting of nanotubes, fullerenes, nanoshells and any combination thereof.
- 34. The method according to claim 1 wherein at least one molecular electronic component is a conjugated organic compound.
- 35. The method according to claim 1 wherein the organic compound is permitted to assemble in a monolayer, multilayer or network comprising nanoparticles and organic molecules.
- 36. The method according to claim 1 further comprising depositing a passivating film over the electronic device.
- 37. The device made according to the method of claim 1.
- 38. The method according to claim 1 wherein depositing a quantity of said second material is carried out in a manner to provide a layer of second material that is thicker than the layer of second material in the area of common intersection of said first, second and third materials.
- 39. The method according to claim 1 wherein the second material is etched in a manner to provide a layer of second material that slopes to a smaller thickness of second material in the area of common intersection of said first, second and third materials.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This nonprovisional patent application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/380,000, filed May 13, 2002.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
[0002] The research carried out in connection with this invention was funded by Defense Advanced Research Projects Agency (DARPA) administered by the Office of Naval Research (ONR), Grant No. N00014-01-1-0657.
Provisional Applications (1)
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Number |
Date |
Country |
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60380000 |
May 2002 |
US |