Claims
- 1. A method for producing a buried heterostructure device comprising the steps of:
- a.) providing a superlattice substrate comprising at least one planar GaAs layer and at least two AlGaAs layers each in juxtaposition with the GaAs layer;
- b.) epitaxially depositing a single crystal germanium layer on the superlattice substrate;
- c.) depositing a gold layer on the germanium layer;
- d.) imagewise patterning and etching away selected portions of the gold and germanium layers;
- e.) encapsulating the superlattice substrate in a compatible, heat resistant encapsulating material; and
- f.) annealing the encapsulated superlattice substrate to attain homogeneous disordering in an uppermost region of the superlattice substrate.
- 2. The method of claim 1 wherein the superlattice substrate comprises a plurality of alternating GaAs and AlGaAs layers in a sandwiched configuration.
- 3. The method of claim 1 wherein the superlattice substrate comprises 2 to 100 alternating GaAs and AlGaAs layers in a sandwiched configuration.
- 4. The method of claim 1 wherein each GaAs layer has a thickness in the range of about 20 to about 500 Angstroms.
- 5. The method of claim 1 wherein each GaAs layer has a thickness in the range of about 20 to about 200 Angstroms.
- 6. The method of claim 1 wherein each AlGaAs layer has a thickness in the range of about 10 to about 200 Angstroms.
- 7. The method of claim 1 wherein the epitaxial deposition of the germanium layer on the superlattice substrate is conducted at a temperature of from about 350.degree. C. to about 450.degree. C.
- 8. The method of claim 1 wherein the depositing the gold layer on the germanium layer is conducted at a temperature of from about 100.degree. C. to about 150.degree. C.
- 9. The method of claim 1 wherein the germanium layer has a thickness ranging from about 200 Angstroms to about 500 Angstroms.
- 10. The method of claim 1 wherein the gold layer has a thickness ranging from about 100 Angstroms to about 250 Angstroms.
- 11. The method of claim 1 wherein the annealing of the encapsulated substrate is conducted at a temperature of from about 300.degree. C. to about 350.degree. C.
- 12. The method of claim 1 wherein the annealing of the encapsulated substrate is conducted for from about 2 to about 30 hours.
- 13. The method of claim 1 wherein the encapsulating material is silicon nitride.
- 14. The method of claim 1 wherein the encapsulating material is silicon dioxide.
GOVERNMENT INTEREST
The invention described herein may be manufactured, used and licensed by or for the Government for governmental purposes without the payment to us of any royalty thereon.
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|
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|
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|
Non-Patent Literature Citations (2)
Entry |
Deppe et al, "Atom Diffusion and Impurity-Induced Layer Disordering in Quum Well III-V Semiconductor Heterostructures", J. Appl. Phys. 64(12), Dec. 1988. |
W. D. Laidig, et al, Appl. Phys. Lett. 38, 776 (1981) in disorder of an AlAs-GaAs SL by impurity diffusion. |