Claims
- 1. A method of making a self-aligned static induction transistor comprising the steps of:
- fabricating a silicon substrate having a top surface and a bottom surface;
- forming an active area on the top surface of the substrate;
- forming a guard ring surrounding the active area;
- forming source and gate regions on the substrate;
- forming self-aligned deep trenches in the source and gate regions
- wherein each trench has a top surface and a bottom surface and wherein said trenches in said source regions are relatively narrow and said trenches in said gate regions are relatively wide;
- forming maskless self-aligned gate metallization in the bottom of said trenches;
- depositing a layer of plasma nitride on the surface of the transistor to completely fill the relatively narrow trenches in the source regions and partially fill the relatively wide trenches in the gate regions;
- planarizing the plasma nitride layer whereby contacts are opened to the gate metallization in the gate region;
- forming source metallization on the source region; and
- forming a drain contact on the bottom surface of the substrate to complete the self-aligned static induction transistor.
- 2. The method of claim 1 wherein the step of forming the self-aligned deep trenches comprises the steps of:
- forming an oxide layer on the source and gate regions;
- forming a polysilicon layer on the oxide layer;
- forming a second oxide layer on the polysilicon layer;
- forming a self-aligning mask on the second oxide layer; and
- etching trenches in the source and gate regions using the self-aligning mask.
- 3. The method of claim 1 wherein the step of forming maskless self-aligned gate metallization comprises the steps of:
- depositing a first layer of metal to make contact with the gate regions in the trenches;
- depositing and planarizing a layer of photoresist on the surface of the first layer of metal; and
- etching the first layer of metal to a predetermined depth below the top surfaces of the trenches.
- 4. The method of claim 1 which further comprises the step of depositing a passivation layer on the source and gate metallizations.
- 5. The method of claim 2 wherein the step of etching the trenches comprises the step of anisotropically etching the trenches to produce relatively vertical walls of the trenches.
- 6. The method of claim 1 wherein the step of forming source and gate regions on the substrate comprises the step of implanting and diffusing N.sup.+ dopant ions into the substrate.
- 7. The method of claim 6 wherein the step of forming maskless self-aligned gate metallization further comprises the steps of:
- growing gate oxide in the trenches;
- forming a P-grade layer adjacent the bottom of the trenches; and
- depositing P+ dopant ions into the P-grade layer to form the gate regions.
- 8. The method of claim 7 wherein the step of depositing P.sup.+ dopant ions comprises the steps of:
- implanting P.sup.+ dopant ions into the P-grade layer; and
- annealing the implanted P-grade layer.
- 9. The method of claim 2 wherein the step of etching the trenches comprises providing a variable sidewall trench oxide thickness to provide for higher or lower breakdown voltages according to the thickness, and wherein a thicker layer of thermal oxide along the sidewalls allows for a more graded gate junction.
- 10. The method of claim 3 wherein the step of etching the first layer of metal comprises overetching the first layer of metal by a factor of 100 to 300 percent.
- 11. A method of making a self-aligned static induction transistor, said method comprising the steps of:
- fabricating an N.sup.- silicon layer on an N.sup.+ silicon substrate;
- forming an active area on the substrate;
- forming a guard ring surrounding the active area;
- forming an N.sup.+ layer in the substrate that comprises source and gate regions of the transistor;
- forming an oxide layer on the N.sup.+ layer;
- forming a polysilicon layer on the oxide layer;
- forming a second oxide layer on the polysilicon layer;
- forming a self-aligning mask on the second oxide layer;
- etching trenches into the source and gate regions using the self-aligning mask wherein said trenches in said source regions are relatively narrow and said trenches in said gate regions are relatively wide;
- forming gate regions at the bottom of the trenches in said gate regions;
- depositing a first layer of metal on top of the transistor to make contact with the gate regions;
- depositing and planarizing a layer of photoresist on the surface of the transistor;
- etching the first layer of metal to a predetermined depth below the top surface of the trenches;
- depositing a layer of plasma nitride on the surface of the first layer of metal to completely fill the trenches in the source regions and partially fill the trenches in the gate regions;
- planarizing the plasma nitride layer whereby contacts are opened to the first layer of metal in the gate regions;
- depositing a second layer of metal on the transistor to make contact with the source and gate regions;
- depositing a passivation layer on the second layer of metal; and
- forming interconnection pads that connect the first and second layers of metal.
- 12. The method of claim 11 wherein the step of etching the trenches comprises the step of anisotropically etching the trenches to produce relatively vertical walls of the trenches.
- 13. The method of claim 11 wherein the step of forming an N.sup.+ layer in the substrate comprises the step of implanting and diffusing N.sup.+ dopant ions into the substrate.
- 14. The method of claim 11 wherein the step of forming gate regions at the bottom of the trenches comprises the steps of:
- growing gate oxide in the trenches;
- forming a P-grade layer adjacent the bottom of the trenches; and depositing P.sup.+ dopant ions into the P-grade layer to form the gate regions.
- 15. The method of claim 14 wherein the step of depositing P.sup.+ dopant ions comprises the steps of:
- implanting P.sup.+ dopant ions into the P-grade layer; and
- annealing the implanted P-grade layer.
- 16. The method of claim 11 wherein the step of etching the trenches comprises providing for variable sidewall trench oxide thickness to provide for higher or lower breakdown voltages according to the thickness, and wherein a thicker layer of thermal oxide along the sidewalls allows for a more graded P.sup.+ gate junction.
- 17. The method of claim 11 wherein the step of etching the first layer of metal comprises overetching the first layer of metal by a factor of 100 to 300 percent.
Parent Case Info
This application is a continuation-in-part of patent application Ser. No. 08/402,786, filed Mar. 13, 1995, abandoned.
US Referenced Citations (4)
Continuation in Parts (1)
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Number |
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402786 |
Mar 1995 |
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