Claims
- 1. In the fabrication of an MOS electrically programmable read-only memory cell wherein a layer of polysilicon is formed insulated from a substrate, said layer being used to define a floating gate member for said cell, an improvement comprising the steps of:
- forming an oxide layer of a predetermined thickness over said polysilicon layer;
- forming a silicon nitride layer over said oxide layer;
- etching said silicon nitride layer, oxide layer and polysilicon layer so as to define a dimension of said floating gate member;
- subjecting said substrate to an elevated temperature so as to grow an oxide region at edges of said floating gate member such that a thicker oxide develops at said edges of said floating gate member when compared to said oxide layer at the central portion of said floating gate member;
- whereby said edges of said floating gate are protected by a thicker oxide region thereby reducing undesirable loss of charge from said floating gate member to overlying structures.
- 2. The process defined by claim 1 wherein said first oxide layer is grown to a thickness of approximately 400-500 .ANG. thick.
- 3. The process defined by claim 2 wherein said oxide at said edges of said floating gate member is grown to a thickness of approximately 700 .ANG..
Parent Case Info
This is a divisional of application Ser. No. 196,838, filed Oct. 14, 1980, now U.S. Pat. No. 4,412,310.
US Referenced Citations (7)
Divisions (1)
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Number |
Date |
Country |
Parent |
196838 |
Oct 1980 |
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